0 Replies Latest reply on Jun 26, 2010 6:05 AM by eng.marwa_ahmed

    verilog to netlist translation error , calibre v2lvs

    eng.marwa_ahmed

      hi

      i'm in an asic project .
      we use tsmc 090 standard cells.
      we generated rams using artisan !
      we use synopsys design compiler (synthesis)
      first encounter(layout)
      calibre(lvs , drc etc)

      to perform post layout simulation on modelsim , and verilog to spice netlist translation using calibre v2lvs , we enter the verilog file generated by the first encounter , and the standard cells verilog library, but we have a problem with the rams :

      Warning: no module declaration for module ram_128_3 first encountered in module DSR_artisan_3_0

      and the module DSR_artisan_3_0 reports a lot of errors in the form :
      Warning: DSR_artisan_6/DUAL_SRAM calls array of unknown dimension DB in undeclared module ram_128_2


      also the pads outputs errors in the form :
      Warning: top/Data_in_PAD insantiates new port C in undeclared module PDC0204CDG_33
      and :
      Warning: positional call to undeclared module PCORNERG_33 in top - pin order will match verilog call.

      no ideas ?
      consider it as if u are making post layout simulation (it is the same idea)
      how to resolve that ram problem ? also pins of the pads undefined ?

      thx for your help