Your input file to extraction (GDS) has several layers in it (as I understand your description). The layers which you want to use for your extraction are the bands generated by the CSI command, which I woudl guess you outputted with a DRC CHECK MAP statement. Let's say you created layers 99.1 for the "minimum" band line and 99.2 for the "maximum" band line. Now for your extraction, you need to decide if you want to use 99.1 or 99.2 for your input layer. Let me point out that I am making several assumptions about your run to make this reply, because I'm not entirely sure what you did for the extraction.
If you use the 99.2 layer, you will get worst case capacitance, and if you use the 99.1 layer, you will get worst case resistance. If you created the CSI layer for "nominal", then you will have the typical spice case.
First of all, many thanks for your quick reply. I considered what you explained to me in your answer, but I'm still having problems to properly run the PEX using the LFD design kit. Let me first describe what I'm currently doing.
1) I've created the CSI layers of the active, metal1, metal2 and poly layers using the LFD command as it is explained in the LFD user guide for two optical conditions DFDD (best case) and DFND (worst case)
2) Then for each optical condition, I have created a file (let me called them output_DFDD.oas and output_DFND.oas) where I put into its corresponding csi layers previously obtained (using the option DRC CHECK MAP) . Then what I have at this point is:
Layers contained: CSI_active_DFDD, CSI_poly_DFDD, CSI_metal1_DFDD and CSI_metal2_DFDD
Layers contained: CSI_active_DFND, CSI_poly_DFND, CSI_metal1_DFND and CSI_metal2_DFND
3) Since this layers does not represent a complete layout, I add to this files all the other necessary layers for this technology to create a transistor (coming from the original layout). I added to this files, the implants, wells, vias, contacts, etc. The only thing that I do not copy into the layout is the pin labels. (maybe this is producing my error afterwards??)
Then, comes up where I'm stucked, I can not perform the PEX with this oasis files that I've created.
What I do is simple, I just use one of this files as a layout input for the PEX, however the PEX stops suddenly saying that there is nothing in the layout and I can not understand why is this happening.
I attached to the email the PEX transcript so you can see what is going on and i also attach to the email a pitcture showing how I use the oasis file as an input to the PEX. If you need any othre information in order to be able to answer me back just let me know and I will give it to you.
Thanks in advance for your help.
I think I see the issue now, but not sure. I believe you are using the layers incorrectly. The reason I say this is that you are outputing the ACTIVE and POLY CSI layers for input to the PEX deck. This would be incorrect. To jump back to the beginning, the two commands are "Contour Simplification Gate" and "Contour Simplification Interconnect". You would use the CSI command only for interconnect layer, such as metal. The CSG command will analyze the appropriate contour inputs from active and poly and return to you the calculated gate "L" and "W" for the spice netlist. Then you (typically with PERL) would substitue those measurements for the drawn measurments in a flat spice netlist for your layout. You would use the CSI layers for the metals instead of the drawn metal layers for extraction.
I would do your flow in the opposite direction as well, IMHO. I would add the CSI layers for the metals into your original layout file, using a different datatype. Then use this new "original" layout file for your PEX and point the metal layers in your PEX deck to the new layer.datatype for the CSI layers. This way, you know that all you need for the extraction is in the input layout file. You do not input the active and poly CSI layers in this method.
Hope this helps, Bill
First of all, many thanks for your quick reply, thanks to your comments I've finally been able to perform my PEX with the lithography contourns obtained by using CSI/CSG information obtained when usind the LFD calibre kit.
My main problem was that the calibre was not properly understanding the oasis file that I was creating with the CSI layers (I don't yet why, but it is no important actually). So what I did it is what you suggested: I extracted my layout into a function.calibre.db database and then using the original file I swap some layout layers for its respective CSI layers. Then using this new original file into the PEX flow I was perfectly able to perform my PEX.
In the other hand, I do not understand why you suggested to me not to add the CSI layers of POLY and ACTIVE to the new original layouts, there is two reasons that I think I should add them:
1) If I want to obtain a clean LVS when performing the PEX (The PEX is also doing a LVS when calling the PEX from calibre) I need to add the poly and active, so my netlist (which I created following the guidelines of your really helpful video using the CSG files) and my layout has the same transistor sizing.
2) The parasitic extraction utilizes the poly and active layers to obtain the capacitances and resistances of the layout. I did my PEX simulation by using the original layout but changing only the interconnection layers (Metal1 and Metal2) and changing the interconnect layers, the poly and active and I got different PEX results as I was expecting.
I do not know if you have any comment about this. Anyways, many thanks for your help again.
For the poly and active layers going through CSI, it's not that it is not possible, it is more that most people didn't bother to do such detail work as yourself. If you consider the interconnect capacitiance and the inter-layer capacitance (such as contact - poly), then using CSI for these layers is a great idea. You must be very careful that the LFD kit you have is going to produce post-etch contours and not just printed contours if you are going to use this mode for CSI. Typically (but not always), the poly and active layers have a much greater etch bias applied to the litho OPC as compared to metal layers, and thus can not be ignored. Please be cautious on this issue.
Glad to hear your run completes now. Thanks, Bill
Last time I asked here how to solve a problem with the LFD, and your comments helped me a lot, so I'd like to continue this thread hoping that you can give me a hand with some new issues.
Overview of the situation:
I am a layout designer and I would like to characterize my layouts using hspice (e.g. extracting delay and leakage consumption) by using the CSG information provided with the LFD kit. Therefore, I can predict my circuit behavior more accurately. By the way, I am using BSIM4 transistor model.
I read on the calibre LFD manual (version 2007.2 and 2008.3) that the transistor gate length provided with the CSG files is computed using this formula:
Leff = LDRAWN + XL -2dL which considers variations of lithography (mask), etch, bias and physical effects.
Thus the CSG gives you just one L for characterization.
On the other hand, I was taking a look on some literature references [1-4, detailed below] and I read that some people is using two different transistor gate lengths extracted from lithography to perform its characterization. More especifically, they are using one gate length for leakage simulations (IDS OFF) and another gate length for delay simulations (IDS ON).
- Can I use the single Leff obtained with the CSG for doing both delay and leakage characterization? Would be the result accurately enough?
- Is the LFD considering this reference knowlodege so they decided to provide just one single L? If yes, does this Leff is related to delay or leakage behavior?
- Should I use a specific transistor model that using the single L provided with the CSG, it automatically modifies the the transistor gate lenght depending on characterization purpose?
Sorry, if I'm questioning too much, but I am really interested of kwowing if I am properly using the lithography information in my characterization.
Many thanks for your valuable help in advance
 W. J. Poppe, L. Capodieci, J. Wu, and A. Neureuther, “From poly line to transistor: building BSIM models for nonrectangular transistors,” SPIE,vol. 6156, 2006.
 Sreedhar, A.; Kundu, S.; , "On modeling impact of sub-wavelength lithography on transistors," Computer Design, 2007. ICCD 2007. 25th International Conference on , vol., no., pp.84-90, 7-10 Oct. 2007
 Cao, K.; Hu, J.; , "ASIC design flow considering lithography-induced effects," Circuits, Devices & Systems, IET , vol.2, no.1, pp.23-29, February 2008
 Singal, R.; Balijepalli, A.; Subramaniam, A.; Chi-Chao Wang; Liu, F.; Nassif, S.R.; Yu Cao; , "Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.18, no.4, pp.666-670, April 2010
First let me say that the version(s) of Calibre you are addressing are back a few years, when the whole concept was under development (2007). In those days, the leakage model for SPICE was considered unreliable. For our work, we only focused on Ion for timing analysis because people where bandgaurding the off current power calculations dramatically, and although they didn't like it, they weren't will to invest in this type of effort. What they wanted to know was the effect of timing due to new lithography techniques. So, bottom line, the version of CSG you are referring to is for Ion only.
Next, and more important, I believe the interpretation from our manual is not right for the formula. The formula you quote is the one from the SPICE manual which we used as reference. What this version of CSG is designed to do is to combine (LDRAWN + XL) into one variable, Leff. However, we might of documented it incorrectly in the manual, or it got lost in translation. This is why we put the value of XL to "0" when we substitue Leff for LDRAWN. The other characteristics of the SPICE model are still in play.
Last year, a new version of CSG, call it CSG 2.0 was experimented with. This version uses a calibration table (LUT) which is created from the SPICE model itself, and make a pass at outputing both a Leff and Weff which would be good for both Ion and Ioff. Initial experiments were good.
But the basic problem still remains. This is what we discussed last time, and is more pronounced in smaller technologies such as 28nm gate. That is, it is very difficult to simulate the poly etch process, and you need this number to get a correct answer.
Many thanks for your response. As you said I was using an old version of the lfd kit. For instance, the etching model does not appear as an option in the old version of the LFD kit that I was using, but it does in new ones. So, I will update the version of the LFD kit that I'm using (I'm going to add the mentor tools from 2010-2011 that we have available at my university) and I will try to run my simulations again. About the etching model, my PDK lithography kit was not considering this, (I was using the FreePDK provided by the NCSU university that is free available on internet in order to learn how the lithography simulation works and how to configure the complete flow, before starting using a real lithography kit from ST). Therefore, I will try to take into account the etching process in the near future.
Thanks again for your help.