Problem with PEX when using CSG/CSI information with LFD lithography simulations

Discussion created by sgomez on Jul 8, 2010
Latest reply on Oct 25, 2010 by sgomez


I'm working with the LFD (Litho-Friendly Design) kit from Calibre and  I'm having troubles to run the parasitic Extraction xRC.

My objective is to extract the parasitic extraction from the  lithography simulations instead of getting it from the layout view. In  order to do so that's what I am currently doing.

1) Creating the layout
2) Generate the CSI/CSG layers using lfd design rules and put this  layers (jointly with the contour simulations) in a gds file (let's  called it test.gds)
Note: I check out this gds file using a free gds viewer and they seem  to be created (the pvbands and the csi bands)
3) By using the CSG layers I'm obtaining an spice netlist (trest.sp)  that contains the "real" dimensions of the transistors. By real I  mean, the transistor width and length expected for each transistor  when simulating the pvdbands.
(In this video there is an explanation of how to do so:
3) I run the parasitic extraction using the spice netlist "test.sp"  and I use as a layout input file the gds file "test.gds".

Then when I run the parasitic extraction the calibre PEX extraction  tool says that there is nothing in the layout. Like it is not  understanding the gds file because of layers where wrong mapped or  sthg else.

So, if anyone knows which is the correct flow to perform the parasitic  extraction from the contour simulation using the litho-friendly  designs rules, I would really appreciate your help.

Thanks in advance for your help.