daniel.ibanescu

LVS logic gates matching

Discussion created by daniel.ibanescu on Jul 20, 2010
Latest reply on Jul 21, 2011 by unni.sreedharan

Hi,

Can someone please help with an explanation, solution for the folowing problem?

 

Running LVS on spare logic gates (gates tied together, common power and ground rails, floating outputs) containing nand2, nand3, nor2, nor3, inverter (2= 2 inputs, 3= 3 inputs), i have the following report:

 

 

2    1(689.800,723.600)  MN(nch)                               inv2/mn1  MN(nch)
       l: 1 u                                                    l: 0.5 u                     100%
       w: 2 u                                                    w: 1.1 u                    81.8%

 

10    24(705.850,744.700)  MN(nch)                              nand25/mn1  MN(nch)
       l: 0.5 u                                                  l: 1 u                        50%
       w: 1.1 u                                                  w: 2 u                        45%

 

8    18(702.350,687.900)  MN(nch)                              nand22/mn1  MN(nch)
       l: 1.5 u                                                  l: 1 u                        50%
       w: 2.5 u                                                  w: 2 u                        25%

 

15    38(714.600,723.600)  MN(nch)                              nand35/mn1  MN(nch)
       l: 1 u                                                    l: 1.5 u                    33.3%
       w: 2 u                                                    w: 2.5 u                      20%

 

I pasted just o portion of the report to present the problem. Left is layout, right is schematic.

 

Although the reduction is made properly, the device identification is not done considering the device properties (i think!..) I am expecting to see a perfect matching with smashed mosfets warning but doesn't happen.

I am running flat LVS without gate recognition.

 

Thanks !

Outcomes