9 Replies Latest reply on Jul 21, 2011 1:39 AM by unni.sreedharan

    LVS logic gates matching

    daniel.ibanescu

      Hi,

      Can someone please help with an explanation, solution for the folowing problem?

       

      Running LVS on spare logic gates (gates tied together, common power and ground rails, floating outputs) containing nand2, nand3, nor2, nor3, inverter (2= 2 inputs, 3= 3 inputs), i have the following report:

       

       

      2    1(689.800,723.600)  MN(nch)                               inv2/mn1  MN(nch)
             l: 1 u                                                    l: 0.5 u                     100%
             w: 2 u                                                    w: 1.1 u                    81.8%

       

      10    24(705.850,744.700)  MN(nch)                              nand25/mn1  MN(nch)
             l: 0.5 u                                                  l: 1 u                        50%
             w: 1.1 u                                                  w: 2 u                        45%

       

      8    18(702.350,687.900)  MN(nch)                              nand22/mn1  MN(nch)
             l: 1.5 u                                                  l: 1 u                        50%
             w: 2.5 u                                                  w: 2 u                        25%

       

      15    38(714.600,723.600)  MN(nch)                              nand35/mn1  MN(nch)
             l: 1 u                                                    l: 1.5 u                    33.3%
             w: 2 u                                                    w: 2.5 u                      20%

       

      I pasted just o portion of the report to present the problem. Left is layout, right is schematic.

       

      Although the reduction is made properly, the device identification is not done considering the device properties (i think!..) I am expecting to see a perfect matching with smashed mosfets warning but doesn't happen.

      I am running flat LVS without gate recognition.

       

      Thanks !

        • 1. Re: LVS logic gates matching
          chris_balcom

          Are you able to text one of the floating outputs in the layout, and add a top level name on the same net in the source to match?

           

          Another idea is to use LVS CPOINT. You may need to use hierarchical LVS for that experiment though, so you can use hierarchical pathnames to get down to those floating output nets.

           

          Are there just a few spare logic gates, or many? Using a higher LVS PROPERTY RESOLUTION MAXIMUM may help if there are lots of spare logic gates.

          • 2. Re: LVS logic gates matching
            daniel.ibanescu

            The idea was to leave the outputs floating, unconnected, and not mark them as ports. This solution would help Calibre to identify them based on ports name but would require to name the outputs individually and carry the text to top level.

             

            The hierarhical LVS is not applicable, we don't have a license for that, only flat.

             

            BUT solution no3 worked thank you !!!

             

            I highly appreciate you help. Thanks again. First time I bump into this problem, probably until now I had fewer than 32 spare logic gates.

            • 3. Re: LVS logic gates matching
              chris_balcom

              That's a nice way to start the morning! Thanks for sharing the good news.

               

              • 4. Re: LVS logic gates matching
                daniel.ibanescu

                 

                Now i see the warning in the previous LVS report, it says clearly Warning: LVS property resolution maximum exceeded... didn't noticed it before

                • 5. Re: LVS logic gates matching
                  chris_balcom

                  And I didn't think to ask about that warning either. Thanks for taking the time to add that observation.

                   

                  As more and more Calibre users find out about this community and add their questions and comments it should become more and more valuable.

                   

                  Just for grins I went to google.com and searched for this:

                   

                       calibre lvs spare logic gates errors

                   

                  And your thread came up as the top result. I think that's neat... anyone around the world can use google to search for a Calibre problem or question and they might find threads that you or I were discussing publicly. I know it's not a substitute for SupportNet or official documentation but as an extra thing that is available to everyone that wants to help each other I think it's pretty cool.

                  • 6. Re: LVS logic gates matching
                    daniel.ibanescu

                    Glad I can help ...and receive.

                    Anyway i didn't expect to receive an answer so soon, but after spending almost a day to debug this i gave up and called upon other users knowledge... glad i did.

                    • 7. Re: LVS logic gates matching
                      unni.sreedharan

                      Hi,

                       

                      Thanks for the solution.

                       

                      I was also facing the same issue, where can i specify this particular switch?

                      Currently i am using LVS PROPERTY RESOLUTION MAXIMUM ALL(in calibre rule file), still i am getting the the issue.

                       

                      Thanks,

                      Unni

                      • 8. Re: LVS logic gates matching
                        daniel.ibanescu

                        Hi,

                         

                        I think you can check first, in the report at "LVS Parameters", if the command was applied correctly, check the number for "LVS PROPERTY RESOLUTION MAXIMUM". And check for any other warnings also.

                        If you still have the problem it could be another cause.

                         

                        As a note from SVRF Manual :

                        Note that there is a potential performance penalty for specifying large property resolution

                        maximum values. In particular, the ALL keyword should be avoided.

                        • 9. Re: LVS logic gates matching
                          unni.sreedharan

                          Hi,

                           

                          Thanks for that quick reply, let me check it.

                           

                          Unni