I have a need on a current design which contains 3 routing layers (layers 1-3) and one ESD protection layer (layer 4). My issue is that for most of the design I need to use partial vias so I can keep the ESD layer as large as possible. However due to the thickness and hole size of the via there is not enough of a hole to PCB thickness ratio for the PCB vendor to stop their drill at the correct depth (i.e. layer 3) without making contact with the last layer (i.e. will most likely short the via to the ESD layer). The solution that was presented was to "back-drill" these holes from the ESD layer side and fill with inert epoxy, therefore removing the connection of the partial vias to the ESD layer. This all sounds good in theory, however this presents another problem, massive dendritic growth issues at the point where the exposed ESD copper layer edge meets the epoxy (i.e makes the connection between layers anyway). The solution obviously is to not have exposed copper next to the epoxy. That means that I need to pull back the copper on the ESD layer slightly larger than the hole size on the ESD layer to allow for a clean back-drill operation.
This is where my question arises:
I have set up a partial via in PADS (layers 1-3), however I also need to add an "antipad" to layer 4. But because PADS sees the end layer as layer 3 it ignores any pads/thermals/andipads beyond this point. Does anyone have any ideas how to get around this issue with PADS?
And no there are way to many vias to manually add a keepout over each and every via on layer 4. And why would I even want to try something like that in the first place, move a via forget to move the independent keepout. I am then as equally screwed as just letting the dendritic growth happen.
If you are going to be doing back-drill from the ESD layer, can you make all vias THRU hole with a small pad bigger the drill diameter on ESD layer? Then you flood your ESD layer that will produce clearance to a pad of the via on ESD layer. Back-drilling operation will remove the pad and barrel part of the via up to layer 3.