3 Replies Latest reply on Feb 20, 2012 7:40 PM by yubaobaobao627

    Parasitic EXtraction of a layout without schemtic source


      Hi all,

      I am trying to create an interconnect capacitance in my circuit.
      So I created a schematic view with only the PINs (PLUS and MINUS) and I created the layout of the cell.
      My aim is to extract the parasitics for having a schematic to use in simulations.
      The problem is that, when I try to run the Calibre PEX (as for the LVS), I get:
      "ERROR: Nothing in source.
      ERROR: Nothing in layout. "
      How can I solve the problem of extracting the parasitics from my cell?