5 Replies Latest reply on Nov 23, 2010 12:17 PM by Mentor_Per_Viklund

    Embedded Components

      We are working on some embedded components , we are using the Optimizer tool
      in Expedition 2005.
      Something is wrong , for a 1.5pF capacitor the calculated area
      is too big (78660.4 square mils for a interdigitated capacitor). For the material we are using BC12TM the
      capacitance density is 6 pF/mm2, so the calculated area will be about 400
      square mils to get 1.5 pF.
      Anything we missed to do? How do we set a correct  layer stackup?
      Which are the real and correct sizes for the different forms of capacitors:Interdigitated, Mezzanine, Printed.
      Would you explain the process we need to follow to get correct results?
      Attached are some pictures with the data we are working.



      Thanks in Advance.

        • 1. Re: Embedded Components

          I think there is a couple of things going on.


          You are talking about interdigitated capacitors and your optimizer dialogue screenshot also shows this type of capacitor

          ...but your process editor screen shot shows the settings for a screen printed plate capacitor type so I can't see your settings for interdigitated capacitors.


          That said....


          The capacitance density stated for FaradFlex BC12TM (I believe 0.72nF/cm2 = 7.2pF/mm2 at 1GHz) is for a plate capacitor with two equally sized square shaped capacitor plates with BC12TM in between.


          The interdigitated capacitor basically uses the fringing capacitance between the  capacitor fingers and is very dependent upon the metal thickness and above all ; VERY low capacitance density compared to a plate capacitor.

          Hence, an Interdigitated capacitor is compared to a plate capacitor *very* large.


          For an in detail discussion and a formula of interdigitated capacitor value, check out the IEEE Transactions on Microwave Theory and Techniques vol 44 no 6 June 96 and there, the paper "CAD Models for Multilayered Substrate Interdigital Capacitors" by Spartak S. Gevorgian, Torsten Martinsson, Peter L.J. Linner and Eric Kollberg.

          I can't attach the paper due to copyright but you can search and down load  from IEEE.org


          Also, the layer thickness in the layer stackup for the dielectric is set to 20th and BC12T is just 12um  equal to appr 0.5 th




          Per Viklund

          1 of 1 people found this helpful
          • 2. Re: Embedded Components

            Thanks for the reply Per Viklund





            I´m doing a little example layout with two components  a resistor and a capacitor  i will put the resistor on layer 3  and a capacitor on layer 5.

            How do I set the layer stackup with the materials that I´m going to use?.

            How do I set for example a Ohmega ply material in one layer and the BC12TM on another.

            I just need to define their thickness?

            In the fabrication outputs  what parameters do i need to enable (Gerbers files, etc)?



            I ve been searching and there is no a basic tutorial with at least one simple example  for working with embedded passives.





            Thanks in Advance.

            Ramón Medina.

            • 3. Re: Embedded Components

              Hi Ramon,

              Sorry for late answer.



              First, your resistors need to have Value, Tolerance and PowerRating properties defined.

              For example:





              To use the Ohmega Ply resistor technology:

              First review the settings in the "Setup=>Material / Process Editor"

              The settings we ship are examples only but good enough for testing. -For a production run, you need to verify the settings with your manufacturer.


              The process contains settings for how large the resistor pads should be and how the resistor definition mask should be sized.


              The material settings control the sizing of the resistor with respect to component value and tolerance.

              Larger resistors  can be made to sharper tolerance and also allow for laser trimming if needed.


              Also define design rules for resistors in CES  (or Set up Parameters)

              There is a complete set of spacing rules that applies to embedded resistors. such as:

              Resistor body - resistor body spacing

              Resistor body - resistor mask etc.


              Next, you open the "Setup=>Embedded=> Planner"

              This tool let you evaluate various selected resistor materials  against component values to help you pick the materials that are right for your design (= small component area and most number of embedded parts)

              This tool does NOT alter your design in any way -it is just a planning tool!

              You select the materials you consider and the spread sheet and graphs shows which resistors that can be embedded and which ones can't (as their dimensions would become unrealistic)

              This step can be bypassed if you already have made up your mind about which parts to embed and what materials to use!


              From the "Planner" you can go to "Optimize"

              You can also use "Setup=>Embedded=> Optimize" but if opened from the planner, the Optimizer will use the selected settings from the Planner by default.


              The "Optimizer" is the tool that actually creates the embedded cells for you.


              Start by defining which layers to use for embedded and what material to use for each layer. -Typically you have only one resistor layer ($$$$)

              Click on the "Layers"-tab

              Enable the desired material for the desired layer.

              You CAN have more than one material on the same layer (unusual for thin film though)

              Apply your settings!


              Next, click on the "Resistors"-tab

              To select parts to embed: Chose "View by -RefDes"

              In the lists, select the resistors to be embedded.


              Once selected, you are back in the Optimizer Resistor Tab:

              You can select the desired resistor geometry or geometries such as "Rectangular" and/or "Serpentine"

              ...and you can select the desired material(s) 


              The Optimizer will generate one embedded cell for each resistor for each selected geometry (resistor form) and for each selected material....and for each layer if more than one!


              Hence, for 100 resistors, 2 forms and 4 materials you get  100 x 2 x 4 = 800 permutations


              You can now manually select the resistor you want in the spread sheet and the preview will show you its cell.

              Clearly doable if there are just a few or if you want manual control for a chosen few.

              ...But if you have 2000 permutations, you can click on the "Optimize" button to have the Optimizer pick the most optimal permutation for each refdes.

              It will either try to achive smallest component size -or, fewest number of materials (cost reasons) if more than one material is defined.


              At this point, we have still NOT altered your design!

              The embedded cells are all created in memory and has not yet been written to your design.


              Click the "Apply" button to have the on board resistors replaced with the just created embedded resistors.



              In the Gerber Output dialogue, you have the option to include resistor features onto your films.


              For Ohmega Ply which is a  "Subtractive Thin film process" you need one film which is the normal artwork for the layer AND the resistor bodies all mereged as one film.

              -Hence, for that layer, opt to include the resistor bodies of hte chosen material.

              In addition, you need a separate film with the "Resistor defenition mask".

              There is a setting in the output dialogue to only output these masks.


              You also need to generate IPC-D-356 A or B output. The manufacturer will use that to verify resistance values and tolerances.






              Embedded capacitors:

              Now THIS is a whole different ball game.....

              You can use BC12TM as dielectric and it will allow you to design an embedded Capacitance Plane

              -that is a power plane with higher capacitance  between power/ground. -notching magic -just ordinary design but with a high tech material in the stack up.


              To replace discrete capacitors with embedded capacitors:

              The process is pretty much the same as for resistors. -there is a Capacitor tab in the Planner and in the Optimizer.


              issue here is to chose the appropriate capacitor type.

              We support:

              Interdigitated -this looks like 2 interleaved forks.

                 Typically only used in GHz range Microwave applications where you need *very* small capacitance values.

              Screen printed  -Screen printed or ink jet printing of dielectric and conductive inks to form a layered structure

              Mezzanine -This is the Motorola Mezzanine process involving a photo polymer dielectric and deposit thin film metal.

                    -rather high capacitance values but few shops can do these and it requires a Motorola License.






              • 4. Re: Embedded Components

                Thank for your answer Per_Viklund.


                We already finish our design , at the end we followed the steps you just describe.

                So we only had a little problem , we used the mezzanine form in the expedition tool.


                It suppose that the mezzanine capacitor is a planar capacitor.

                So the construction of a capacitor is like this:



                Layer 1 to layer 2 blind via to access the top plate

                TOP PLATE

                DIALECTRIC (Material BC12TM Faradflex or any other material)

                BOTTOM PLATE



                So the issue is that when the tool creates the capacitor it only show to us the next information:


                Layer 1 to layer 2 blind via to access the top plate( the via is not shown on the layout and it is not reported on the drills drawing  it is only seen on the generated NCD Drill file called Layer2-mezzanine )

                TOP PLATE (This is not shown as a plate (square form) instead is a circular pad. This will be the pin 1 of our capacitor

                DIALECTRIC (This is ok we enable it in a user layer called material and output it on the gerber files)

                BOTTOM PLATE( This is ok , it is shown  like a plate (square form) This will be the pin 2 of our capacitor


                We fixed the problem creating a Conductive Shape (square form with the respective area needed) and connecting it to the Top Plate (circular pad) , then connecting it to a blind via .


                Is there an issue  on the software the we still don´t know?

                Or everything is ok and thats the normal way to build that kind of capacitor ?



                Best Regards.

                • 5. Re: Embedded Components

                  Glad to hear that you have made progress.


                  What you've done should be OK.


                  The mezzanine capacitor is a bit special in that the capcitor plate is an extra layer added with deposited thin film in between PCB layers.


                  Check this image from CIrcuitree:



                  Circuitree article here: http://www.circuitree.com/Articles/Cover_Story/04562bfccafe7010VgnVCM100000f932a8c0____



                  This capacitor uses a photopolymer additive dielectric and then a vapor deposit of thin film metal. (or thick film)

                  The via you see, is actually a micro via  going from the signal layer down to the thin film to connect to the capacitor plate.


                  Layer wise, having one of these on Signal 2 you will have:



                  Dielectric layer between sig1 and sig2

                  Thin film metal capacitor plate (connected with micro via to signal 1

                  Photo polymer dielectric



                  The bottom capacitor plate is hten on Signal2 while the top capacitor plate is not really on any layer -just a manufacturing mask.

                  The article above explains in detail.


                  However, the actual plate should also be visible (-it is possible to output on Gerber.)

                  There should be a specific setting in Display control to manage this: Under hte "Layers" -tab you have "Conductive Materials" and there I guess Partec_RD21 is a possible mezzaninen material.


                  That said, you can probably use the same construct "cheating" by adding a conductive shape as you did in order to use standard dielectric. -You need to double check the capacitance calcualtions in that case though.

                  Also, if there is a specific type you need that we don't support, you can request it on the MentorIdeas site.