We are working on some embedded components , we are using the Optimizer tool in Expedition 2005. Something is wrong , for a 1.5pF capacitor the calculated area is too big (78660.4 square mils for a interdigitated capacitor). For the material we are using BC12TM the capacitance density is 6 pF/mm2, so the calculated area will be about 400 square mils to get 1.5 pF.
Anything we missed to do? How do we set a correct layer stackup?
Which are the real and correct sizes for the different forms of capacitors:Interdigitated, Mezzanine, Printed.
Would you explain the process we need to follow to get correct results?
Attached are some pictures with the data we are working.
Thanks in Advance.