1 Reply Latest reply on Nov 22, 2010 7:57 AM by samantha_lizak

    Resistance extraction issues


      I have a calibrated deck with 4 switching filed profiels. I have the corect vertical capacitance extracted, as weel as the fact the i see the nets. But i can't see the resistance ot non of the nets. The structures i use to test are about 300um long and about 10um wide. The min dimensions for all my stack metals are 2um widht and 2um spacing. If i specify max lenght and max width some of the resistance is showing but is incorect and it not applies on the entire net. I need what is causing this issue?




        • 1. Re: Resistance extraction issues

          Hi Angel-


          I can at least suggest some paths to check, although without a log file or anything I'm working in the dark.  First, all prereqs covered:

          • There are rules for resistance (I assume so, since you can sometimes get it)
          • Nets have power and ground  (no power, no current flow --> no parasitic resistance): you generally don't see resistance on test structures, for example.
          • The SVRF file identifies power and ground; that is, you tell Calibre which way things are flowing.


          Now, things that can cause snags in a file that looks good on the surface:

          • Mismatch between declared precision/magnification/resolution and intended DBU size. You might be seeing numbers that look off because 5 dbus is being interpreted as 5 microns rather than 5 nms, for instance. The SVRF commands Precision, Resolution, and Layout Magnify all interact.
          • You have multiple resistance rules defined. This can happen when there is a maze of INCLUDEs or #ifdefs controlling what file gets used.
          • Portions of the layout are somehow being excluded. This can happen with LVS Box, PEX Exclude (or Include) Net, or badly chosen xcells with hierarchical extraction.
          • The net may be picking up other names and the resistance is being reported elsewhere. (Less likely, because for simple nets such as you would use for testing your setup it is usually all or nothing.)
          • The net has a short or an open in the layout. If you have a clean LVS run (we do recommend not even trying xRC until LVS is clean), are the layer statements and connectivity rules identical?  If you haven't run LVS (perhaps no source schematic), try tracing the net in DRV/RVE or running a point-to-point resistance check on some intermediate spots. Make sure you have the correct Connect By statements to pass power between metal layers. 


          Hope that helps-