I am new to IC design using Cadance. I finished my layout and now trying to run LVS and PEX using Cadance. To run Calibre LVS, I first exported the schematic netlist from Export -> CDL_OUT option.
Then I included this file as my source netlist in the LVS setup.
When I run LVS I am getting the following Warnings.
WARNING: There is no data for layout net name __USER_DEFINED_LVS_POWER_NAME__
WARNING: There is no data for layout net name __USER_DEFINED_LVS_GROUND_NAME__
WARNING: Invalid PATHCHK request "GROUND && ! POWER" : no POWER nets present, operation aborted
WARNING: Invalid PATHCHK request "POWER && ! GROUND" : no POWER nets present, operation aborted
WARNING: Invalid PATHCHK request "! POWER && GROUND" : no POWER nets present, operation aborted
Is it possible to know how to clear these warnings?
Also, now when I run the PEX simulation I get the following errors
ERROR: There is no usable returns path nets in the PDB for inductance extraction.
ERROR: Net information could not be built.
ERROR: The inputs for inductance engine were not properly built.
I also get the warnings same as warnings in LVS. The above errors are related to parasitic Inductor extraction. I am not sue whether it because of the warning in LVS.
Can somebody help me regarding this?
Thanks a lot!!!