1 Reply Latest reply on Nov 30, 2010 10:29 AM by chris_balcom

    can we black box a cell in  LVS


      Am getting the following Error, as there is no subckt defination available right now with me for abc module, would it be possible to black box this module for now.



      Error: No matching ".SUBCKT" statement for "abc" at line 1138054 in file "../xyz.cdl

        • 1. Re: can we black box a cell in  LVS

          The following statement would cause cell "abc" to be boxed from the layout during connectivity extraction and comparison. It would also cause subcircuit "abc" to be boxed from the source during comparison but there would be a problem in the case you described, because the subcircuit "abc" doesn't exist in the source cdl to begin with.


          I'm not aware of a way to have an empty subckt (similar in nature to black box cell for Calibre) be created on the fly in place of missing subcircuits.


          Would you be able to manually create an empty subcircuit definition in the cdl file using the same pin names that would be found from using this statement in the rulefile during connectivity extraction?


          LVS BOX "abc"


          A possible flow might go like this:


          1)   Create netlist from the layout, using the LVS BOX statement as above.


          2)   Note the pin names for the "abc" cell in the netlist from layout extraction.


          3)   Manually create an empty cubcircuit in the source netlist for "abc" using the same pin names as found in the layout netlist.


          4)   Perform LVS comparison between the layout netlist and the source netlist (no need to repeat connectivity extraction unless the layout changes)