Here is information from Tech Note MG80489 on SupportNet.
The Impedance Parameters under High Speed Design Rules will not be used by Layout
or Router (Auto or Interactive Routing). However, some High Speed rules (Min/Max length,
Stub length, Match length) are used in Router. Verify Design in Router doesn't perform
Electrodynamic Checking (EDC), it's done by Layout’s Verify Design only. The Router does
not automatically adjust the trace width to impedance nor does it recommend a trace width.
Mentor tools with that support this are ICX, and Hyperlynx. ICX is only available with Expedition
and Board Station. Hyperlynx is supported in PADS.
Impedance calculations are embedded, and proprietary. There is no option to change which
plane is referenced. The Impedance calculations are not affected by the plane’s shape. These
calculations produce a general impedance value.
PADS uses Diff Pair gap value and the two nearest planes (Cam or Split/Mixed) to calculate
trace impedance; if the trace goes between two planes (Stripline), or just one trace to the nearest
plane (Micro Stripline) in other case. Cut outs are ignored for both cases.
For correct reporting of trace impedance, you must set "No plane" for ALL routing layers that do not
have specific plane area shapes defined, this includes Top and Bottom.
The thickness dialog box, trace width, Diff Pair gap are the only inputs to the impedance calculation
users have. If you have the EDC (Electrodynamic Checking) option you can set extra rules, under the
high speed rules. EDC module ignores all Split/Mixed layers that do not have drawn plane areas
shapes and regards these layers as Routing/Signal layers instead.
Example: 4 layer design would be to verify the Layer Definition that Top and Bottom are set to "No Plane",
while Inner 1 and Inner 2 are set to Cam or Split/Mixed, select a specific net, then RMB>Properties, should
report some Zohm value. Now changing the trace width the impedance changes correctly.
Best approach is to work with Signal Integrity Engineer and Board House to figure the best trace width
and board stackup combination to achieve required trace impedance. There are plenty of impedance
calculators on the web; PADS calculated values are only close estimates.
For example: On terminals L13.1 to U10.13 PADS Layout reports a capacitance of 0.04pF when it's selected.
While the calculation of just the pads 0.020"x 0.024" is cap of 0.22pF.
1. Pads are included with trace for total net capacitance.
2. The values are given by numeric field solver are used to get both impedance and capacitance
(and delay), which come from layout data (trace parameters and stackup). Numeric field solver is a
special module of PADS that is responsible for calculating electrical characteristics of segments and
copper areas. The method is based on numerical algorithms for solving integral equations for surface
charge and current.
Tech Note MG80489 also has some links to information in the User's Guide that may be helpful.