Is there any experience that RC extraction show an abnormal result when two transistors shared the same substrate or well?
The port is in the most left hand side and two transistor are placed at below picture:
I expected the R for for VDD to T1 should be smaller than VDD to T2.
However, both R are just a little bit different only.
So I think that there may be some problem which caused by share the well.
Is there any bothers could help?
Hi Andrew. Does your well have sheet resistance associated with it? Since well resistance is very high compared to metal resistance, the dominant effect should be the metal1 resistance. But if the resistance is almost the same, maybe the well is getting shorted out, instead of having very high resistance through it.