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DDRx controller timing model...

Question asked by yashoda.narvankar on Dec 24, 2010
Latest reply on Dec 29, 2010 by yashoda.narvankar




I am performing DDRx Batch Simulation for Octeon processor and DDR3-1333 interface. The timing models required for DDR3 are fine, but I need to make a timing model for the controller as per my controller specs....


I referred to App note 10706 (Creating Hyperlynx DDRx Memory controller Timing Model), but still have doubts in some parameters as some details given in controller datasheet matches few paramters given in each of the 3 examples given in the application note. Also there is no timing diagram given in the datasheet. Can anyone help me with this thing?


I am attaching the controller parameters given in the datasheet.


Thanks in advance.