It is obvious, that there is no need to keep special clearance rule to such short trace. It enough to keep only default manufacturing rule (4-5 mil). So for dense boards we can get mach space by taking short traces out of special clearance DRC rule given for the whole class (clock for example). There may be many such traces on layers, so for now the only possibility is to draw rule aria around them. The problem is to maintain all this frames and keep in mind to move them if trace moves (what can happen a lot during the design flow). And even more, sometimes we have to design another board that based on existing data, but the routing might be completely different, and forgotten rule aria frame may lead even to significant mistakes. My solution is to give possibility to connect special DRC class rule to trace length. So if I set trace to trace rule 25 mil I would be able to determine the minimum length to obey it. All shorter traces will obey to default rule.