i've been simulating a DDR3 interface by means of the DDRx wizard. The interface consists out of 1 controller and 4 memory devices. Address/Cmd are connected using flyby topology. In the controller there are 2 clock drivers which are routed in a T-branch.
For the Third and Fourth RAM some hold-time margin errors occur.
In the DDR_report_data_violations_xxx.xls the Min Hold Time (column Q) is calculated by subtracting the initial delay from the simulated holdtime.
If I remove the initial delays from the IBIS model (by means of the command remove initial delays in the visual Ibis editor) I still see the same figures after simulating.
I've expected my Min Hold Time to be equal to the Hold Time since the initial delay has been removed.
Is this a correct assumption?
Is there a difference between initial delay and initial delay delta (mentioned in column Q) ?
If so, what is the difference and how is the initial delay delta calculated or where is it retrieved from?
thanks in advance,