I will create a service request for this issue through customer support.
Can you tell me if this one was resolved? If so, what was the outcome?
I'm also having issues with DDR3 Read fails on the wizard, which I have logged an SR for, but I'm curious as to whether this might help.
I don't recall what happened with this case. DDR Wizard problems are usually caused by wizard setup errors, IBIS models being incomplete or wrong, or controller timing model errors.
Hello - given that the DQ signals are edge aligned with the DQS on a Read operation from a DDR3 SDRAM, does it even make sense to specify a setup time? They are both changing state on the same time boundary. If we were talking about setup time relative to the clock (phase shifted by0.25*tck) inside the DDR3 Controller, a set up/hold time would be more applicable.
Did this SR ever get anywhere? I too am doubting the calculation inside the spreadsheet. I agree the Initial Delta Delay is applicable for control/address lines relative to the CLK or for DQ lines relative to a DQS on a write. But the read operation behaves a little different. Usually the data is stable before setup and hold times are calculated. For a DDR3 read, the data lines are changing state during a DQS transition.
Unless I missed something... please set me straight!
You are correct that the read operation timing is difficult to understand. I think this application note will help.
The read setup and hold times are usually defined at the internal register of the controller where the strobe signal is already delayed by 1/4 clock cycle. If your controller data sheet specifies the timing relation at the pins, then there is a provision in the timing model syntax to specifiy that. In that case, the setup time is usually a negative number, indicating that it happens after the strobe edge at the pin. The setup time is still before the delayed strobe edge, though. When reviewing your timing margins, you can find the receiver waveforms in the results folder. Compare the DQ to the DQS(delayed) to calculate the setup and hold times for the read operation.
The initial delay delta is still applicable on the read operation because the DQ and DQS signals are not exactly aligned. Ideally, they are, but there is always some skew allowed. That small skew that happens in real life is what causes the initial delay delta.
What is simulation onffset for read sigal ,
whats it significance, i have gone through the manual 10685
it is negative still the signal has cleared the read pass test ?
Kindly Elaborate .
We are unable to access the above mentioned appnote.Please check that issue.