6 Replies Latest reply on Dec 14, 2011 5:52 PM by chris_balcom

    TRACE PROPERTY COMMAND

    Stefan.Keil

      Hi,

       

      i have a problem with a property error in LVS. The LVS shows an error in a resistor with an amount of 0.00514%. I want to get rid of these error.

      i found that the trace property command can do zhis, but i want to know how it operates.

       

      TRACE PROPERTY R(res_poly)          r r <x>

       

      what means the number that i can set for <x>? I thougth it was a failure in percent but my runs told me that that would b not right.

       

      run 1: x = 0.005 i got no error

      run 2: x = 0.0005 i got the error

       

      can anyone help me?

       

      Best regards,

      Stefan

        • 1. Re: TRACE PROPERTY COMMAND
          chris_balcom

          Hi Stefan,

           

          I can help with that. What percentage of difference would you like to allow between layout and source, without triggering an error? If you would like to allow a difference between layout and source of 2% on the L property of MN devices then you could use the following statement:

           

          TRACE PROPERTY MN L L 2

          • 2. Re: TRACE PROPERTY COMMAND
            Stefan.Keil

            Hi Chris,

             

            many thanks for that.

             

            So my conclusion for the two testruns was wrong or there is an inaccuracy.

             

            best regards,

            stefan

            • 3. Re: TRACE PROPERTY COMMAND
              nagaraju.juloori

              May i Know in which situation we will allow to have different W/L  for the devises in the layout and netlist,

              basically am from ASIC PnR background, so was with an assumption that both layout and netlist should match witout any exception.

              • 4. Re: TRACE PROPERTY COMMAND
                chris_balcom

                There are likely several different reasons that a little bit of "wiggle room" may be desired when comparing the W/L of devices from layout to source. I can think of only a few right now. Maybe other people with recent experience might share some general thoughts on this. Slight variations in the result of property calculations depending on the layout configuration is one thought. Another possiblilty might be devices in processes that allow angles on gate regions, the final calculations for W and L may not be precise enough to allow strict checking with zero tolerance when the inevitable binary roundoff related to angled edges comes into play.

                • 5. Re: TRACE PROPERTY COMMAND
                  nagaraju.juloori

                  hi Chris,

                  Thanks for the replay,

                  So what i got from your replay is, the wiggle room for the mismatch comes from the rounding off in the calculations, so can i assume that the accracy % should be around 1%, if not generally how much will be there.

                  got more qns there

                  Does this comes from the fab, or design, std cell- vendor   dependent.

                  • 6. Re: TRACE PROPERTY COMMAND
                    chris_balcom

                    Hi Nagaraju,

                     

                    I think we need input from other users to get a fuller understanding. My thoughts were just possibilities, I'm not sure that's the main purpose these days.