I can help with that. What percentage of difference would you like to allow between layout and source, without triggering an error? If you would like to allow a difference between layout and source of 2% on the L property of MN devices then you could use the following statement:
TRACE PROPERTY MN L L 2
many thanks for that.
So my conclusion for the two testruns was wrong or there is an inaccuracy.
May i Know in which situation we will allow to have different W/L for the devises in the layout and netlist,
basically am from ASIC PnR background, so was with an assumption that both layout and netlist should match witout any exception.
There are likely several different reasons that a little bit of "wiggle room" may be desired when comparing the W/L of devices from layout to source. I can think of only a few right now. Maybe other people with recent experience might share some general thoughts on this. Slight variations in the result of property calculations depending on the layout configuration is one thought. Another possiblilty might be devices in processes that allow angles on gate regions, the final calculations for W and L may not be precise enough to allow strict checking with zero tolerance when the inevitable binary roundoff related to angled edges comes into play.
Thanks for the replay,
So what i got from your replay is, the wiggle room for the mismatch comes from the rounding off in the calculations, so can i assume that the accracy % should be around 1%, if not generally how much will be there.
got more qns there
Does this comes from the fab, or design, std cell- vendor dependent.
I think we need input from other users to get a fuller understanding. My thoughts were just possibilities, I'm not sure that's the main purpose these days.