Couple releases back we have introduced a special type of Copper for shorting two or more electrical nets. Electrically of the schematic they are still have it's own identity like GND, AGND, PGND, etc.
Once you add the piece of Copper and got into Properties to add the Net it will belong, you will see a newer feature called Bridge. Once you select Bridge, you will be able to assign to that copper multiple net names.
Benefit of this is that Clearance Check will not flag you with an error and Connectivity will see individual Nets not shorted.
Long before PADS introduced the 'bridge' method I developed a 'jumper' component that is a short on the board with two independent nets on either pad. I like it better because it does show the connectivity on the schematic. While it does cause clearance errors, these are easy to filter through because all of my 'by design' clearance errors will be on components with "JU#" reference designators. I archive a 'clear.lst' report when I release a design, so that I can verify I don't have additional errors when a layout is revised.
If you are interested in this approach I'll post my jumper component and decal.
I like to see how other designers handle problems. I'd like to have a look at your jumper component/decal solution to this one if you'll post it!
I believe this is everything you need to import this part into your library. This is a jumper with pads matching an 0805 component. If I need to separarate the traces I can cut the trace in between and install an 0805 for whatever impedance I need.
In my clearance report I'll see this:
Error 1 Location 1374.23,2136.62 Level 1
Distance between pads too small:
JU7.1, JU7.2 overlapping
As long as I see the pads are on a component with a JU ref des I know it is a non error.
Comments and questions welcome.
I have also done the same thing with (back in the day) Cadnetix, thru Dazix thru VeriBest to Expedition, and on Altium also probably same method as jwheeler.
I just made a few of them to match trace width I was connecting with.
But all you are really doing is creating a decal that is made up of two overlapping pads. Yes you will get
and error but they are easy to see & move on to real errors. I made a few of them so that the pad sizes were exact same width as
the trace I was connecting together, say 10mil, 15mil, 25mil, 50mil wide, then length as short as possible or needed.
That way when done within a trace you see the ref des but other than that it looks like it is just a contiguous trace only.
In tying two plane areas together you could still use the same thing, using it as the bridge trace between planes.
If you didn't want these pads as exposed copper you have to remember to set soldermask pads to 0 or - the size of pad pending cad system used.
Thanks to all!
Bridging copper was what I was trying to remember.
I do also use components to do this on the board, to allow it to be shown on the schematic. In this case, we were trying to emulate what we had done with copper tape, without showing it on the schematic, so the bridged copper did the trick.
One thing I had hoped would be different with bridged copper was the IPC-356 netlist. I have to open all of the shorts, whether made through overlapping pads or bridges, to run artworks for an IPC-356 netlist comparison in my gerber editor. Kind of risky to run the check, then go back to the version with all fo teh shorts closed.
I was concerned about this too, but with 9.3, and possibly earlier, I didn't check, the PADS generated IPC netlist is correctly amended to report the copper bridged nets as a single re-named net.