If you can get either a Touchstone S-parameter model or a SPICE model of the transformer then you can use that to simulate your net in HyperLynx. There are technotes and application notes on SupportNet to help you understand the steps for this. The HyperLynx user manual is quite helpful, too. Generally, the bigger problem is getting an adequate model of the IC.
Thanks you Weston,
I don't have enough time to read much documents right now...
So I got a "SPICE" model of one transformer in pdf.
Is there some easy way what shall I do with it to be able to use it as fast as possible in HyperLynx SI?
H5007model.pdf 32.8 KB
Copy-paste it into the text file and you'll have a SPICE model. In HL there is a component (connector?) into which a SPICE model can be mapped.
I thaugh the same and did it.
I saved the file with extension sp , I saw it in "Assign Package" dialog but this model doesn't have any ports.... see my picture. Not possible click OK button.
What I did wrong?
SPICE_MODEL_MAPPING.JPG 24.0 KB
Any success simulating the giga ethernet?
Simulating GigE is no different than 10/100 BASE-T as long as you have the proper models.
Please see the attached sample EZWave waveforms. All the simulations have been performed using HyperLynx v9.0 Beta 3.
Thank you for your replay.
In some variations 1G ethernet works on 5 levels of voltage. I have a previous version of HyperLynx and I'm not familiar with v9.0. Is there a model to generate those levels?
You are right, 1000Base-T uses PAM5 differential line signaling with more than five voltage levels (+1, +0.5, 0, -0.5, -1 and more due to the other end TX), while 100Base-TX uses MLT-3 differential signaling with three voltage levels (+1, 0, -1). The block encoding is 4B/5B in the case of 100Base-TX and 4D-PAM5 in the case of 1000Base-T. However when you perform Time Domain characterization of the link there is no way to know if the response is adequate or not, if you use random stimulus. This is why the IEEE Std 802.3 defines four Transmitter test modes for 1000Base-T compliance tests. These modes are enabled by setting bits 9.13:15 if the device is equipped with a GMII interface. The Standard defines also the core tests that one should use for compliance measurements:
· Differential output template tests
· Peak differential output voltage level and accuracy tests
· Droop tests
· MDI Return Loss
· MDI Common-mode output voltage test
· MASTER/SLAVE Jtxout measurements
· Bit Error Rate verification
· Data rate
For each of those tests there are limits that you can check against. Please see the standard for more details.
For simulation purposes, usually behavioral buffer models can output test mode 1 and 2 stimulus. Test mode 1 stimulus is useful for measuring output amplitudes, amplitude symmetry and pulse drop.
You can also perform Frequency Domain simulations of the channel (MDI Return Loss). The spec defines the following limits:
· ≥ 16 dB from 1MHz to 40 MHz
· ≥10-20LOG(f/80)dB from 40 MHz to 100 MHz, where “f” is in MHz.
I have attached for you an example of a plot that shows the MDI differential return loss (SDD11). You can use “Targets” (HL v.9.0) or “Guidelines” (HL v. 8.2) to help you to visually check against the limits.
If you have the real hardware you can use Tektronix Ethernet Compliance Test Software (TDSET3) installed on an oscilloscope to perform those tests either in TD or FD. I have attached few sample waveforms from measurements for your convenience.
I hope this helps,
Thank you very much Cristian. You have been a great help.
I will look into it.
Do you happen to know if there is a way to get a simulated eye pattern?
As far as I know you need a modulated random-data pattern to generate en eye pattern of a PAM-5 signaling and I guess that this is not easy to implement in Spice (and match the real silicon behavior). I personally haven’t yet come across those types of models.
However maybe somebody from Mentor has a better answer to this question.
I'm trying to perform some simulations of a Ethernet 100-base-T or 1000-base-T channel, and I cannot get an ibis model for the differential physical layer side of those transceivers, the models only include the MII/RMII interface and control signals.
By contacting the mentor support, I got the following answer:
"Ethernet uses multi-level signaling, so we don’t really simulate it in HyperLynx (although I guess you could set up a SPICE simulation in HyperLynx to do it).
If it is a SERDES link inside a switch or something, it works like any other SERDES bus.
For most applications, though, Ethernet routes are extremely short on the board, and actually somewhat “forgiving” (since it will run over 100m of twisted-pair cable).
Because of this, most Ethernet simulation work, if any, is done on the S-parameter level, looking at things like insertion loss, return loss, and crosstalk. I believe Ethernet has some specs for these that need to be followed on the board level. You can use HyperLynx to extract S-parameters to compare to the spec"
Did any of you managed to perform simulations in this case?