How to check LVS for such layout?

Discussion created by 51tz on Jun 27, 2011
Latest reply on Jun 28, 2011 by Govind_kulkarni

Hi Guys, below is a portion snapshot of sub-block layout from P&R tool.  Stdcell places back-to-back in each cellraw and power/gnd rail alternative supply stdcell.


For each power/gnd rail, VDD and VSS pin generated at the line end as illustrated left side, which is used to connect power/gnd net at top-level.


When run LVS by Calibre,  those VDD and VSS extracted as separated ports, thus port number is not matching source's (note: source only has tow powre/gnd ports: VDD and VSS)


So, how to have Calibre indentify rail pin VDD and VSS as only two ports?