Is this for a lower level cell, during a hierarchical run?
Lower level cells usually get their pins only because there are connections from devices in the cells, up to something outside the cell like top level ports or devices in other cells.
In the LVS report, was it just the one discrepancy for the missing connection? Maybe just for the source, or just for the layout? Or were there different discrepancies for missing connections in both the layout and source?