Why Calibre identifies the line-end as "Pin"?

Discussion created by 51tz on Jun 29, 2011
Latest reply on Jun 29, 2011 by chris_balcom

Hi Guys,  I failed LVS check, afterwards, I clicked RVE to locate the first error (3 missing connection) to see what happened. In layout viewer.


Green:   Active area (diffusion area)

Blue:     Metal 1

White:   Via12


Actually, this is a NAND logic gate. After double checked, I make sure all input pins and output pin are connected to external wire.


From that "bold frame" generated by Calibre. I guess Calibre might indicate those 3 line-end of pin "Y" (rectilinear shape with 3 lien end) missing connection,but those 3 ends should connect to active area, especially it really does, no problem! On the other hand, those 3 ends are not "pin", why Calibire identified it as "pin"?


I tried change "LVS SOFT SUBSTRATE PINS  YES|NO", but failed.