2 Replies Latest reply on Aug 4, 2011 6:36 PM by 51tz

    I got such warning after LVS

    51tz

      Hi Guys, I got the warning as below after LVS check, though, LVS passed. I still worry about how such warning turn out?

       

      "Warning: Ambiguity points were found and resolved arbitrarily."

       

      Thanks.

        • 1. Re: I got such warning after LVS
          chris_balcom

          Warnings like that are common with circuits that contain symmetrical portions. Here is an example of a circuit that contains ambiguity:

           

          % cat layout.spi

          R0 in1 1

          M1 1 2 4 N

          M2 1 3 4 N

          R3 4 out1

           

          % cat source.spi

          R0 in1 n1

          M1 n1 n2 n4 N

          M2 n1 n3 n4 N

          R3 n4 out1

           

          The two transistors are interchangeable, no difference is apparent for LVS to tell one from the other. The LVS report will show this:

           

           

          ***************************************************************
                                         OVERALL COMPARISON RESULTS
          ***************************************************************


                                   #       ###################       _   _
                                  #        #                 #       *   *
                             #   #         #     CORRECT     #         |
                              # #          #                 #       \___/
                               #           ###################


            Warning:  Ambiguity points were found and resolved arbitrarily.

          -----------------------------------------------------------------

           

          o Statistics:

             1 net was matched arbitrarily.


          o Ambiguity Resolution Points:

                (Each one of the following objects belongs to a group of indistinguishable objects.
                 The listed objects were matched arbitrarily by the Ambiguity Resolution feature of LVS.
                 Arbitrary matching may be prevented by assigning names to these objects or to adjacent nets).

                 Layout                      Source
                 ------                      ------

                               Nets
                               ----

                 3                            n3

           

          If the gate of either transistor is labeled to match from layout to source, then both transistors will be identified with certainty:

           

          % cat layout.spi

          R0 in1 1

          M1 1 gate1 4 N

          M2 1 3 4 N

          R3 4 out1

           

          % cat source.spi

          R0 in1 n1

          M1 n1 gate1 n4 N

          M2 n1 n3 n4 N

          R3 n4 out1

           

          And the LVS report will be completely clean, no messages about ambiguity:

           

          ***************************************************************
                                         OVERALL COMPARISON RESULTS
          ***************************************************************


                                   #       ###################       _   _
                                  #        #                 #       *   *
                             #   #         #     CORRECT     #         |
                              # #          #                 #       \___/
                               #           ###################


          -----------------------------------------------------------------

           

          I believe that many designs are considered clean even with ambiguity. Some people prefer to avoid ambiguity and take extra care to label nets in layout and schematic to avoid it. I would be very interested to hear from LVS users about their different opinions on the subject.

           

          Hope it helps,

          -chris

          • 2. Re: I got such warning after LVS
            51tz

            Hi Chris, many thanks, very helpful.