1 Reply Latest reply on Aug 15, 2011 3:10 PM by chris_balcom

    How are you supposed to handle SUBCKT globals in calibre LVS that connect to different top level pins

    jonadams

      When trying to run top level LVS on a ASIC chip we had problems handeling globals that needed to be connected to different top level ports.

       

      Example

      ** The VSS from X1 should connect to VSS in the cell top and the VSS from X2 should connect to VSS2 in the cell top

      .GLOBAL VDD VSS

       

      .SUBCKT top  VDD VSS VDD2 VSS2

      X1 POWER_PAD $PINS VDD=VDD

      X2 POWER_PAD$PINS VDD=VDD2

       

      include pads.spi

      .GLOBAL VDD VSS

      .SUBCKT POWER_PAD VDD

      M_1 VDD net_6619 VSS VSS NMOS w=41.6u l=0.13

      .END PVDD1DGZ