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How are you supposed to handle SUBCKT globals in calibre LVS that connect to different top level pins

Question asked by jonadams on Aug 15, 2011
Latest reply on Aug 15, 2011 by chris_balcom

When trying to run top level LVS on a ASIC chip we had problems handeling globals that needed to be connected to different top level ports.

 

Example

** The VSS from X1 should connect to VSS in the cell top and the VSS from X2 should connect to VSS2 in the cell top

.GLOBAL VDD VSS

 

.SUBCKT top  VDD VSS VDD2 VSS2

X1 POWER_PAD $PINS VDD=VDD

X2 POWER_PAD$PINS VDD=VDD2

 

include pads.spi

.GLOBAL VDD VSS

.SUBCKT POWER_PAD VDD

M_1 VDD net_6619 VSS VSS NMOS w=41.6u l=0.13

.END PVDD1DGZ

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