n.ahmad

LVS error in top cell

Discussion created by n.ahmad on Aug 28, 2011

I'm having a problem with my digital design. I'm using CMRF8SF process design kit Calibre LVS in Mentor Graphic v2008.2_9.1.

 

My top cell design is AND gate which using inverter and NAND gate design.
Inv and NAND gate design have clean DRC and LVS, but when I did the layout for top cell which contain inv and NAND layout, the LVS showed an error.

Attached are my schematic, layout and LVS report for your understanding. The error is related to missing instance subc and soft substrate.

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