I am using HyperLynx BoardSim v8.1.1 to translate a Cadence Allegro PCB .brd file into .hyp file. The translation worked fine.
The problem came when I opened the translated .hyp file in BoardSim, which claimed "one or more nets are completely unrouted". Our layout engineer confirmed that the .brd file I was using is a completely routed design, and I myself also confirmed this with the "Unconnected Pins Report" within Allegro. Digging further, I found that the "completely unrouted" nets are mainly Power/Ground nets or related. Anyboady know how to solve this problem? I tried to clean up redundant metals on those nets, but it did not help.
Ignoring this problem, I can still extract channel model in BoardSim and export to LineSim to do simulation. The question is whether the simulation result is still valid? How does the unrouted Power/Gound nets affect the high-speed channel simulation?