This is normal and will not affect your SI simulations. Often, when planes and pours are not translated you will have some guides present on power nets which were fully routed in the layout tool. HyperLynx simulates signal nets based on the assumption that plane layers are continuous structures.
Whenever you translate a PCB design into BoardSim, you should always check the stackup and the power nets. Check that the stackup has the correct layer assignments (signal or plane), and that the layers have the correct properties and thickness. Check that all the appropriate nets are specified as power-supply nets. The routing checker does not check power-supply nets, so the errors should go away after you specify the nets as power-supply nets.