I agree that the 8b10b simulation looks odd. I can't imagine why a specific bit pattern would create the variety of discrete high and low voltages. I expect that the problem is more a function of the pin models. Can you give us more details about the circuit and models to see if we can reproduce the problem?
Please find attached HyperLynx LineSim file. The transceiver simulation models were downloaded from Xilinx website, Virtex-6 GTX transceiver IBIS-AMI models.
The AMI settings used were:
All other Tx/Rx AMI settings are default values (unchanged).
Thanks for the help!
TXP7_X.ffs.zip 9.5 KB
I'll create a service request for you regarding this issue to see if I can figure out the cause.
Thanks for help!
I forgot to say that those two Eye digrams were simulated at 6Gbps. I also simulated the channel at other speeds, say 3Gbps, and results are basically the same as 6Gbps.
The output of the AMI wizard does not show the eye at the pins of the receiver, but shows the output of the receiver AMI model. 8b10b definition ensures that there are never more than 5 bits of the same state, so it is similar to a PRBS-5.
I ran the AMI simulation with PRBS-6 (because there is no option for PRBS-5) and found that the results start to show the same type of distinct voltage levels. There is some function in the receiver AMI model that causes this separation based on the bit pattern. If you need more explanation of why the receiver creates the separate voltage levels, you need to ask the creator of the receiver AMI model.