First, you need to ensure that the nets are associated as a differential pair by correctly assigning an IBIS model with the [Diff Pin] section. Then check that the vias are within the distance defined in the advanced preferences, Differential Via Search Padstack Size Factor.
If the two vias use different padstack names, this configuration does not have a representation in the FFS file syntax, so the vias show up in LineSim as single vias. This situation should be fixed in release 8.2 to correctly export the differential vias to a diff via symbol in LineSim.
For accuracy via model, you may need to run 3D solver for your GHZ channel. I have tried Mentor's Zeland 3D via solver beta, it's an excellent tool and given a very trustable accuracy up to 30GHz.
For Signal-via Modle, This is a license feature for PI.If no this feature, the menu is grayed.
Thanks for very useful info.
I managed to extract differential via model directly from BoardSim, the trick is the pin numbers of the PCB component have to match that of simulation model. As I use Xilinx GTX IBIS-AMI model, I have to change the pin number mannually to match the PCB schematic. One niggle though, the exported free-form LineSim schematic is a bit messy like following:
The differential vias are quite clear now, but the coupled differential track are twisted around. Simulation seems to work though.
The schematic is logically correct, but not visually appealling. There is a simple procedure shown in this technote to make the schematic look nice.
Use Xilinx IBISWriter to create, from your NCD file, an IBIS model specific to your board. Not only will you be able to simulate any net connected to this FPGA without massaging the IBIS file, but you also get the per-pin parasitic values instead of the coarse min/typ/max.
Disclaimer: I routinely do the equivalent of this using brand "A". Brand "X" advertises this capability and I imagine it works as well.