5 Replies Latest reply on Oct 7, 2011 3:12 PM by hai.tran1

    Differential signal simulation with bus switch ...

    hai.tran1

      Using Hyperlynx V8.0, I am having getting a fatal error window stating:

       

      "Line:231,  File:C:\views\mholley_HL8.0_2\hyp_src\bswDiffPair.cpp  File date:Apr 7 2009"

       

      using a DDR3 DQS/DQS~ drivers going through a TI bus switch, TS3DDR3812_RUA, and terminates at a Hynex DDR3 DQS receiver.   What could cause this?  How can I fix this?

       

      Note that,  I have added a DIFF_PIN section to the TI switch IBIS model:

       

      |*******************************************************************************

      |                                   DIFF PIN

      |*******************************************************************************

      |               if diff_pin is needed, you must edit this section

      [Diff_pin]   inv_pin      vdiff        tdelay_typ   tdelay_min   tdelay_max

      |

      4            5            0.400V       0ns          NA           NA

      6            7            0.400V       0ns          NA           NA

      24           23           0.400V       0ns          NA           NA

      22           21           0.400V       0ns          NA           NA

      18           17           0.400V       0ns          NA           NA

      16           15           0.400V       0ns          NA           NA

      |

      |*******************************************************************************

       

      where those pins are connected to respective DQS/DQS~ lines.

        • 1. Re: Differential signal simulation with bus switch ...
          weston_beal

          The series switch model should not have [Diff Pin] section. That device in itself does not have any differential buffer properties.

           

          Also, I'm pretty sure the [Series Switch Groups] is not correctly defined. You should review the IBIS specification together with the device data sheet to figure out the correct data for this section.

           

          There is another potential problem with the pin ordering in the [Series Pin Mapping] section. See this technote for details:

          http://supportnet.mentor.com/reference/technotes/public/technote.cfm?tn=MG541956

           

          Weston

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          • 2. Re: Differential signal simulation with bus switch ...
            hai.tran1

            Hi Weston,

             

            Thanks for the quick response regarding "diff pin".  I forgot to tell you that the "single ended" signal simulation going through the switch works fine.  Nevertheless, per your suggestion in the [Series Pin Mapping] section, I will re-order such that the switch pins are together, e.g.

             

            [Series Pin Mapping]   pin_2                model_name     function_table_group

            |

            2                      41                   TS3DDR3812_A_33_S            1

            3                      39                   TS3DDR3812_A_33_S            1

            4                      38                   TS3DDR3812_A_33_S            1

            2                      42                   TS3DDR3812_A_33_S            3

            3                      40                   TS3DDR3812_A_33_S            3

            4                      37                   TS3DDR3812_A_33_S            3

             

            becomes

             

            [Series Pin Mapping]   pin_2                model_name     function_table_group

            |

            2                      41                   TS3DDR3812_A_33_S            1

            2                      42                   TS3DDR3812_A_33_S             3

            3                      39                   TS3DDR3812_A_33_S            1

            3                      40                    TS3DDR3812_A_33_S            3

            4                      38                   TS3DDR3812_A_33_S            1

            4                      37                   TS3DDR3812_A_33_S             3

             

            I will update you with the result.  In the mean time, I still think I have problem with simulating Differential signal through a bus switch, any suggestions to get around that ?

             

            Regards,

            Hai Tran

            • 3. Re: Differential signal simulation with bus switch ...
              hai.tran1

              Hi Weston,

               

              I still haven't gotten the simulation to work for differential signals going through serial bus switch yet, even though the single-ended signal simulated just fine with the IBIS models I have attached.  Do you know of any working example simulating differential signals going through serial bus switch?  Or is this simply a Hyperlynx bug?

               

              Hai

              • 4. Re: Differential signal simulation with bus switch ...
                weston_beal

                Hai,

                 

                I have an example of a bus switch working in a differential pair. Please open a service request through SupportNet and attach your test case to the service request. That way, we can find what is going wrong in your specific case.

                 

                Regards,

                Weston

                1 of 1 people found this helpful
                • 5. Re: Differential signal simulation with bus switch ...
                  hai.tran1

                  Hi Weston,

                   

                  Thanks for pointing me in the right direction.  I have submitted a service request, SR #2431520099 for this issue.  In the mean time, for my reference, please send me the work example.

                   

                  Thanks again.

                   

                  Hai Tran