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Hyperlynx sees an internal signal layer as a plane layer

Question asked by john.heimlichiii on Nov 16, 2011
Latest reply on Nov 16, 2011 by yu.yanfeng

Hi all,

My coworker is working on a board design where layer 7 of 10 is a mixed layer, it has tracks and several plane areas.

The total copper area for this layer, according to Hyperlynx, is 49%.

Layer 7 is properly defined as a signal layer in the CES stackup editor and in Plane Assignments. The check mark is also on to keep the layers in sync.

Does anyone know why Hyperlynx sees this as a plane layer?

 

Thank you.

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