Is it possible to perform DDR2 timing analysis in linesim by simulating two or more DDR signals simultaneously for e.g. simulating data and strobe or clock and address at a time.
That's a good description of the procedure by Cristian. One additional thing that you need to know is that interactive pin model assignment done in the Assign Models window override the REF file model assignments. Make sure that when you assign part models through the REF file (the correct method in this case) that you remove any pin level model assignments on that part.
Yes, you can do this. You need to use per-pin stimulus to get the correct time offset between the two signals' stimulus and bit patterns. After than you can measure the setup and hold times between the two signals at the many edges. I recommend using an oscillator bit pattern for the strobe (or clock) and PRBS for the data (or address/command/control) signal.
thanx for tour kind reply.
I am having problems in DDRx batch simulations in boardsim. my design includes Micron MT47H64M16 DDR2 memory which is controlled by xilinx Virtex5 FPGA. I am using the ibis model provided by micron for this particular SDRAM but the DDRx batch simulation wizard is showing errors in pin mapping. the wizard is assigning the wrong package model to the memory although the ibis model includes the models for all of the packages provided by micron. my question is why the wizard is not picking up the right component model from the ibis model. do I have to select my particular component from within the ibis model or what??
The models assignment for DDRx Wizard is no different than the one for interactive or batch mode simulation, so yes in case if your IBIS contains models for more components you have to choose the right component for your design. To do that, go to Models -> Assign Models/Values by Reference Designator (.REF File) menu. Then on the Design’s part list section select the memory IC’s that you want to assign models to, check .IBIS/.EBD under the Library section, choose the proper IBIS model from the dropdown list and finally pick the right component from the Components/models dropdown list. Last step, click on the Assign Model button and save the .REF file. DDRx will use this .REF file and will recognize the model assignment that you made here.
what I have understand from the replies is that in DDRx batch wizard the prefared method of model assignment is using the .REF file and after that there is no need to do pin level assignment of each IC in the design. is it so?
I have assigned the IC models using the .REF file but the wizard is still not recognizing the individual pins. do I have to assign pin model to each pin of the IC individually before performing the DDR batch simulation or the wizard perform the individual pin assignment itself?
If you have assigned the models using .REF file, there is no need for per pin assignment. From your description it is really difficult to understand what’s wrong with your setup, but you can try simulating in interactive mode. Assuming that the models and their assignment are correct you should be able to properly simulate.
To debug you can do the following:
1. 1. Disable crosstalk, select a DDRx net and go under Models -> Assign Models/Values by Net. All the drivers, receivers and terminations are listed there and the models should be properly assigned. If not check either your .REF file or IBIS models.
2. 2. Set the proper buffer settings (Input, Output, Output Inverted) and simulate. If everything was ok at 1. you should be able to properly simulate.
3. 3. Assuming that 1. and 2. went well DDRx should properly work.
4. 4. While in DDRx wizard you can double check the models assignment (IBIS Models step -> click on Assign Component Models).
Hope this helps.
I guess that the issue is your memory controller model (Xilinx V5). Did you customized it manually or using ISE tool? If you simply downloaded it from Xilinx website this model is not ready for simulation.
I have followed your mentioned steps. after assigning the ic models by .REF file I go to the Models -> Assign Models/Values by Net . the models for the DDR2 memory are asigned but there is no model assignment for the memory controller that is virtex 5.
I have customized the model manually by uncommenting the particular package from the list of packages and I have also set the C-comp value for output mode for my desired IO standards. are there any more changes to be made to the virtex 5 model??
The IBIS model provided by Xilinx is not targeting a specific device-package combination, but it is just a collection of models for various available I/Os within the V5 family. Consequently the [Pin] section of the model doesn’t reflect a real pin out with proper signal name. This is how this section looks like:
[Pin] signal_name model_name
198 LVCMJED18_F_4_TB_33 LVCMJED18_F_4_TB_33
199 LVCMJED18_F_6_LR_25 LVCMJED18_F_6_LR_25
200 LVCMJED18_F_6_LR_33 LVCMJED18_F_6_LR_33
201 LVCMJED18_F_6_TB_25 LVCMJED18_F_6_TB_25
However after customization your model should match your devices pin out as per your schematic and PCB layout symbols. The customized model will look like:
L19 mcb1_dram_dm(0) SSTL15_OT50_LR_33
M20 mcb1_dram_dm(1) SSTL15_OT50_LR_33
N20 mcb1_dram_dq(0) SSTL15_OT50_LR_33
N22 mcb1_dram_dq(1) SSTL15_OT50_LR_33
K22 mcb1_dram_dq(7) SSTL15_OT50_LR_33
P21 mcb1_dram_dq(8) SSTL15_OT50_LR_33
Another important think is the package modeling. If you use the information contained within the [Package] section that will assign same package parasitic (R,L,C) for every pin (an average for your specific package). That will affect your timing. In order to properly model the package delays (skew) you will need different R,L,C values for each pin. Xilinx provides the package models separately as “*_ibis.pkg” files. You have to add this package model into your IBIS model using [Define Package Model] keyword. Be aware that although this type of package model includes coupling between various pins, HyperLynx will ignore it, but will simulate using the proper delays. The easiest way to customize the FPGA models is by using vendor specific tools (Xilinx ISE in this case), so you don’t have to know too much about the IBIS syntax. If you want to do it manually you can search on Xilinx website and you will find some good documents explaining in detail this process. You might want also to have a look at various appnotes from Mentor as well.
How can i export more than one nets from 8.hyp file to sch? or i need to draw schematic only.
If you want to do a timing analysis for an FPGA, you need to do the following steps:
1) Edit your ibis model of the FPGA, to create the model selector section(s) (example below of a Kintex-7):
[Model Selector] DDR3_ADDR
[Model Selector] DDR3_CTRL
[Model Selector] DDR3_CLK
[Model Selector] DDR3_DQ
[Model Selector] DDR3_DQS
[Model Selector] DDR3_DM
You then need to set the e.g. DDR3_DQS model for each DQS pin (pin section) and do the same for the other groups)
2) Create a timing model for your FPGA controller
This is a more difficult task because it's difficult to obtain the timing information to create a timing controller model in Hyperlynx.
For a processor it's more easy to create your own timing model, because most vvendors supply all the information in their datasheet.
For the memory, you don't need to create a timing model, because you can use the supplied jedec models, included in the Hyperlynx package.
3) If you want to simulatie die-die timing for your DDRx interface, you'll need to set the Timing location statement in your ibis model as well:
Now you can go through the Hyperlynx DDRx wizard and setup your simulation.
I hope this helps.
Not sure if anyone is looking at this thread anymore.
I am having issues with the simulation and I suspect that the IBIS file is the source.
Looking at the difference between the models for SSTL15_DCI_HP_IN40_I and SSTL15_DCI_HP_IN50_I reveals very little difference, so I am wondering if the Xilinx models even really support variation in the termination impedance.
I am thinking that if my 40 ohm system is seeing 50 ohms termination at the Xilinx, it is likely the cause of my ringing issues on the line.
Does anyone have any insight into simulating Kintex 7 with 40 ohm DDR3 traces?
I exported one of the traces to a free form schematic.
If I replace the Xilinx part with a 40 ohm resistor to ground I get no ringing to speak of, so I think that the Xilinx model is not presenting a suitable 40 ohm load at the receiver end.
If anyone has any suggestions as to how to fix this please let me know!
Further to this...
Looking at the waveform at the die appears to be clean also.
So my new assessment is that the package characteristics mean that while it is clean at the die, the signal at the package pin is far enough away from the die connection to have a bad waveform that is not representative of the received signal.
So now if I can only get the DDRx wizard to see it that way...
Sir can you please give some idea to creating timing model for FPGA ?
In FPGA data sheet the exact term for the various time is not mentioned.
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