1 Reply Latest reply on Mar 8, 2012 11:26 AM by weston_beal

    Help regarding DDR3 batch simulation on hyperlynx 8.1.1


      I am running DDR3 batch simulation using DDRx simulation wizard. I am able to meet all the timing constraints with the design but I see all DQ lines overshoots during read cycle,interestingly my design still meet write cycle requirement for undershoot/overshoot. Once I put series termination (22 ohms) on the DQ lines, I can see that DQ lines overshoot/undershoot is under control for read cycle. I just want to know what could be the reason for DQ lines failing during read cycle but not failing during write cycle? Just for the information, I have done write levelling beforehand.

      My rest of the simulation results are passing with good margins so I do not have issue there.

      Kindly share your experience.

        • 1. Re: Help regarding DDR3 batch simulation on hyperlynx 8.1.1

          As you found, the solution is in termination. The problem with series termination is that it should be near the transmitter, but on a bi-directional signal the driver changes. This is why DDR3 uses On-Die Termination (ODT) that can be enabled and disabled dynamically. From the description of your results, it appears that the ODT in your controller is not available, or your simulation setup does not enable the ODT. Look into the controller IBIS model to see if it includes the option for ODT and then verify that your DDR3 wizard setup uses the correct models for ODT enabled configurations.