I am running DDR3 batch simulation using DDRx simulation wizard. I am able to meet all the timing constraints with the design but I see all DQ lines overshoots during read cycle,interestingly my design still meet write cycle requirement for undershoot/overshoot. Once I put series termination (22 ohms) on the DQ lines, I can see that DQ lines overshoot/undershoot is under control for read cycle. I just want to know what could be the reason for DQ lines failing during read cycle but not failing during write cycle? Just for the information, I have done write levelling beforehand.
My rest of the simulation results are passing with good margins so I do not have issue there.
Kindly share your experience.