Setting probe location to die should improve signal.
Also I think driver SSTL15_OT25 or SSTL15_OT50 should be used (symetrical termination, 100Ohm to 1.5V and 100 to GND on chip I presume)
The following classes are defined by standard JESD8-6 from JEDEC:
Class I (unterminated, or symmetrically parallel terminated)
Class II (series terminated)
Class III (asymmetrically parallel terminated)
Class IV (asymmetrically double parallel terminated)
You were right - the probe location needs to be at the die...I'm surprised at how big of a difference that makes. The output termination on the driver does clean up the waveform some more, but the problem was mostly the probe location.
Interesting, I never actually realized what "class I/II" means.
Many thanks for the help. I've been trying to figure this out for quite a while!
I am seeing a similar effect on a SDRAM interface simulation, on DQ lines between an SoC and a DDR3 memory. During READ cycles the simulations are unusable when probed at the pin, but quite OK when probed at the die. If the package parasitics were introducing reflections, I would expect things to be the other way around, the simulation to be OK at the pin, but distorted at the die, after the RLC_pkg.
Playing with LC_pkg values influences drastically the results.
Also, as the SoC model does not contain bonding lengths, Hyperlynx can't simulate the reflections due to improprer probe location.
So why is the waveform so distorted, in effect immediately after the L_pkg?
The RLC packages parasitic behave as a low pass filter which filters out the high frequency noise (removes the glitches on the edges) and this is why the signal at the dies looks cleaner than at the pin. In addition the transmission line is terminated at the die (on-die termination) and not at the pin. Consequently if the proper termination is used all the reflections are suppressed (again at the die). You can plot the transfer function of the filter in HL if you want.
In regards to your comment that HL can’t simulate at the right location, that’s not right. If you are using IBIS models you can use SI/Timing_location keywords to change the location of the probes:
Si_location Die | Optional subparameters to give measurement
Timing_location Die | location positions
[Manufacturer] Dummy Inc.
It should be even easier to choose the proper probe location if you are using Spice models for package parasitics.
Thanks, I didn't know you can plot the transfer function in HL. Wrt to the low pass filter, I agree, it can have that effect on higher frequency ripples, but if you look at the waveforms, the frequency of the reflections are maybe twice or four times the signal frequency. I would expect the reflections to be attenuated, but at the die they are completely gone.
Another point, if the RLC acts as a filter, reducing L to 0 should propagate pin reflections all the way to the die. But when I do a linesim simulation with L=0, I no longer get any oscillations, whether @Die or @Pin. To me that says that it's the RLC_pkg that is creating the oscillations (resonance?), reflecting them back to the driver(?).
About my comment on the probe position, what I meant to say was that without bond length information, if probed at the pin location, HL can't model reflections due to long trace lengths (bond wires), the stub to receiver/ODT has zero length.
The _location statements are useful for the DDR wizzard, but I am just doing scope simulations, and can choose @die or @pin from the GUI.
In the linesim capture:
R1, C1, L1 = RLC_pkg
C2 = C_comp
R3 = ODT
all pasives had their parasitics set to minimum.
The linesim simulation doesn't look as bad as the boardsim, even though I tried to copy all the parameters. Maybe I'm missing some component in the linesim schematic.
The first impedance discontinuity will occur at the output of the DQ driver and the source reflection coefficient can be calculated as Gs= (34-63)/(34+63)= -29/97= -0.298, where 34 ohms is the output impedance of the driver and 63 ohms is the transmission line’s impedance. The second impedance discontinuity will happen at the load, which accordingly to your LineSim topology is a lumped load. Of course the RLC parallel circuit is resonant and will generate oscillations when excited with a stimulus at around the frequency at which the impedance magnitude is at its maximum. When you remove the inductor (L=0) the load becomes almost 62 ohm (considering it resistive). Then the load reflection coefficient becomes Gl= (62-63)/(62+63)=~0. In this case the line is matched at the load, the incoming wave is totally absorbed and there is no reflected wave.
Thank you Cristian, that makes more sense. For the source impedance mismatch, if I add the 29 ohms series resistor, I see less oscillations at package pin, meaning the reflection from the receiver is entirely consumed.
I still have trouble understanding why I don't see the oscillation at the ODT resistor, when my load reflection is not zero (L not 0). In fact, regardless of the RLC values I choose, the signal at receiver is always good (shape changes but no ringing).
As there is no "Len" subparameter in the package description, the RLC values are lumped at the load, so without the concept of transmission line, there is no delayed reflection. What am I missing?