I'm new to HyperLynx and am trying to simulate a data line between an FPGA and a DDR3 memory chip. While the DDR3 write simulation seems to work fine, the read simulation shows severe reflections that I haven't been able to eliminate.
These reflections appear any time the receiver is an FPGA SSTL model. I've tried models from Xilinx, Latttice, and Altera and they all produce essentially the same results. But if I use a Micron DDR3 model for the receiver, then the simulation looks great. I've attached an example in which I start with a Micron DDR3 receiver and then replace it with an FPGA SSTLII model. The length of the transmission line doesn't have a substantial effect on the results.
Given that the DDR3+FPGA combination that I'm modeling seems to work just fine in various evaluation boards, I'm wondering if I'm setting up the simulation incorrectly. I wasn't able to get any guidance from the Mentor Graphics design kits for DDR2 and DDR3, since they all seem to be configured for write simulations only. The tutorials I've seen also seem to cover only write simulations. The same problem doesn't occur in Altium Designer's signal integrity tool, although those results seem somewhat suspect.
Any suggestions would be appreciated!