Is it possible for Valor to check the Pin 1 location of cell when the PCB designer send the tgz file to DFM engineer? Recently we encountered this kind of issue and it seems that valor can not identify the wrong pin numbering in cell. We checked that the VPL library is ok but the cell in PCB is wrong compared with the spec. The two pictures below can show you the details. The VPL library is the same it is in the datasheet.
I am not sure if there is something we missed in the VPL setting or it is hard for VPL to find this kind of issue.