Brian, have you tried adding conductive shapes to your cell on the internal layers?
I don't use RF so I don't know the specifics of that tool, however I have found the conductive shapes layer to be useful for getting planes to pour around non-pcb metal.
I wrote an automation script a while back that I think will do what you describe. For a selected net(s), it creates plane voids on layers adjacent to the via and/or surface pad. The shape of the void is derived from the pad geometry, whether it be a standard shape or custom pad. It supports HDI designs as you can see from the screenshot where it shows the ability to place voids adajcent to core vias and buildup vias in addition to SMD pads.
The voids are static so if you make changes to the layout, you must select the nets you previously ran the script on and regenerate the voids - however you can select multiple nets to run which makes it extremely quick to generate as well as to replace existing voids. You will notice that the form also allows voids to be placed on any number of layers above or below the SMD pad. It will also undercut the pad size using a negative clearance if this is desired.
- use script at your own risk.
- The script uses the mask engine to build the voids, so you will need an automation pro license.
- Nets with plane shapes are ignored (it only processes signal nets). This is by design, but you can easily modify the script to work with plane nets just by commenting out a couple of lines.
The script is part of the AATK toolkit. If you think it will be of use, let me know.
The screenshot below shows a pad to plane clearance on layer 7 of 50mils. Layers 6 and 5 show an undercut clearance of 20mils and 50mils respectively.
Ian and Dale,
Thanks for the replies.
Ian, it sounds like your script would produce results I am looking for, unfortunately we do not have an automation pro license.
Dale, I'm not sure I understand your suggestion. I was not able to create conductive shapes in the cell on internal layers. If this method worked, I would need RF specific cells, and some RF parts would need unique cells as the pinouts or RF connections are not always consistent for a given package style.
I have mislead you.
I suggested using Conductive Shapes, but what I meant was Metallization Area.
Unfortunately the latter cannot be added to internal layers, but Conductive Shapes can (in EE7.9.1).
Conductive shapes won't solve your problem because they add copper whereas you want a copper clearance.
From a plane pouring and DRC perspective, a Metallization Area behaves like real copper, but is not part of the PCB copper.
It is intended to represent conductive but non-soldered areas of placed components. Unfortunately it can only be placed on external layers only. (I guess one doesn't often see such parts placed on internal layers.)