4 Replies Latest reply on Apr 29, 2012 4:13 PM by dale.rebgetz

    RF design - How are you clearing plane metal under component pads?


      Reaching out here to Expedition RF users to see how they handle clearing plane metal under component pads. I’ve submitted idea D8394 which has not seen a lot of activity so I’m wondering if my explanation wasn’t clear or if others don’t need to do this. So if you use controlled impedance RF lines connecting soldered components where the reference plane is a few layers away, I would like to hear from you.


      In many cases we want to replicate a part vendor’s reference design. These reference designs typically are simple construction, two layers with adjacent layer reference planes. Our boards are multilayer with the reference planes 2 or 3 layers away with ground filled in every open space on every layer.


      All RF nets are assigned to a Netclass to ensure consistent clearance to the same layer ground plane. The Group Clearance Rules work great for projecting this clearance through adjacent layers between the meanders and the reference plane. The problem is the plane metal directly between SMT component pads and the reference plane does not get cleared like meanders because component pads can’t be added to an RF group, therefore do not apply to the clearance rule.  This will result in different clearances between the top and intermediate layers…potentially causing performance problems.



      I would like clearances identical from 1 to 2 to 3… With these results we cannot replicate the vendor’s reference design structure and depending on clearances, pad-to-plane coupling can increase capacitive and impedance discontinuities. So, what are others doing about this?


        • 1. Re: RF design - How are you clearing plane metal under component pads?

          Brian, have you tried adding conductive shapes to your cell on the internal layers?

          I don't use RF so I don't know the specifics of that tool, however I have found the conductive shapes layer to be useful for getting planes to pour around non-pcb metal.

          • 2. Re: RF design - How are you clearing plane metal under component pads?


            I wrote an automation script a while back that I think will do what you describe. For a selected net(s), it creates plane voids on layers adjacent to the via and/or surface pad. The shape of the void is derived from the pad geometry, whether it be a standard shape or custom pad. It supports HDI designs as you can see from the screenshot where it shows the ability to place voids adajcent to core vias and buildup vias in addition to SMD pads.


            The voids are static so if you make changes to the layout, you must select the nets you previously ran the script on and regenerate the voids - however you can select multiple nets to run which makes it extremely quick to generate as well as to replace existing voids. You will notice that the form also allows voids to be placed on any number of layers above or below the SMD pad. It will also undercut the pad size using a negative clearance if this is desired.


            Some caveats:

            • use script at your own risk.

            • The script uses the mask engine to build the voids, so you will need an automation pro license.

            • Nets with plane shapes are ignored (it only processes signal nets). This is by design, but you can easily modify the script to work with plane nets just by commenting out a couple of lines.


            The script is part of the AATK toolkit. If you think it will be of use, let me know.


            The screenshot below shows a pad to plane clearance on layer 7 of 50mils. Layers 6 and 5 show an undercut clearance of 20mils and 50mils respectively.


            • 3. Re: RF design - How are you clearing plane metal under component pads?

              Ian and Dale,


              Thanks for the replies.


              Ian, it sounds like your script would produce results I am looking for, unfortunately we do not have an automation pro license.


              Dale, I'm not sure I understand your suggestion. I was not able to create conductive shapes in the cell on internal layers. If this method worked, I would need RF specific cells, and some RF parts would need unique cells as the pinouts or RF connections are not always consistent for a given package style.


              Thanks again,


              • 4. Re: RF design - How are you clearing plane metal under component pads?



                I have mislead you.

                I suggested using Conductive Shapes, but what I meant was Metallization Area.

                Unfortunately the latter cannot be added to internal layers, but Conductive Shapes can (in EE7.9.1).

                Conductive shapes won't solve your problem because they add copper whereas you want a copper clearance.

                From a plane pouring and DRC perspective, a Metallization Area behaves like real copper, but is not part of the PCB copper.

                It is intended to represent conductive but non-soldered areas of placed components. Unfortunately it can only be placed on external layers only. (I guess one doesn't often see such parts placed on internal layers.)