Hi, I'm currently trying to connect the layers of my board using the Via Stitch functionality, but have so far only been able to successfully accomplish it on one part of my design. The attached GIF shows one part of my board. I was able to stitch the upper right corner (a copper area where P8 and P9 connect) with no major issues, apart from having to delete some vias that were giving clearance issues. But when I try to stitch the lower right area (copper for P10 and P11) using the exact same command (right-clicking and selecting Via Stitch), no vias are created- but also, there is no error message, and that in itself is the most frustrating part!
The board itself is a power block where the upper right corner (where stitching works) is a VOUT connection, and the lower corner (stiching not working) is a PGND connection. The only difference in the layer stack-up for these signals is that the bottom connection for VOUT is a Copper Pour, while it is just copper for PGND. All internal layers and the Copper Pour have been flooded:
VOUT (P8, P9): Top (Copper) - L2 (Plane Hatch Outline) - L3 (PHO) - L4 (PHO) - L5 (PHO) - Bottom (Copper Pour)
PGND (P10, P11): Top (Copper) - L2 (PHO) - L3 (PHO) - L4 (PHO) - L5 (PHO) - Bottom (Copper)
Note that this is my first design, and it's quite complicated as a starter, so it's very possible I'm missing something obvious here.
So, any ideas?