1 2 First Previous 23 Replies Latest reply on Apr 6, 2017 6:47 PM by aimee

    Hyperlynx Plane  Noise Simulation

    Karthik.Subramaniam

      In Plane  Noise Simulation How to  Calculate  AC Model for IC Pins,Can  you Explain in brief

        • 1. Re: Hyperlynx Plane  Noise Simulation
          cristian.filip

          Well this is a very good question that unfortunately can’t be answered briefly. Actually the AC model shouldn’t be calculated (it would be too complex) but simulated into a full system simulation bench that is made of die and package driver/receive PDNs along with the PCB’s PDN. The current flow is different for various systems depending on the IC stage and technology involved. For example the current flow is different if you are looking at an IC core, a pre-driver stage or an IO stage. It is also different if you look at a single-ended interface vs. a differential bus. For a single-ended interface the termination scheme will make the difference.

           

          If you have IBIS models for your drivers and receivers you can use in LineSim a black box symbol instead of the regular built in symbols and then you can expose the supply pins through and I/O buffer element (B-element in HSpice, _IO_ element in ELDO). The Spice statement power=off will enable the Spice engine to simulate the current drawn from the power supply and if you add to this circuit all the non-idealities like package parasitic, power supply output inductance/resistance and the PDN impedance (S-parameter) then you will be able to get a better representation of the AC current at any location. You will need also the right stimulus pattern to get even closer. Don’t forget that the currents flow in loops, so the return paths should be included into this picture. Typically this is done by using S-parameter models that have ports for both power and signal nets. That would also include coupling between TLs and PDN.

           

          For core logic PI analysis usually the concern is when the system wakes up or goes to sleep, so step pulses would be good enough.

           

          This is in a nutshell how you can find the shape, amplitude, rise/fall times and any other parameters for your AC Models, but again there is much more to be explained.

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          • 2. Re: Hyperlynx Plane  Noise Simulation
            Karthik.Subramaniam

            thx cristian,

             

            can  give me an simple example of this one  then  it`s clear for me

            • 3. Re: Hyperlynx Plane  Noise Simulation
              cristian.filip

              First of all let’s clarify that for a core logic or pre-driver stage the current distribution is confined into a small region underneath the chip. The current will flow from power supply to ground pins, so TD or FD co-analysis of the chip, package and PCB would be enough.

               

              However for I/O stages the current distribution is not localized anymore and it involves the driver, the receiver and the channel that links them. In single-ended interfaces, the drivers are usually push-pull while for differential interfaces they are current-steering.

               

              For simplicity we can take a simple example of a push-pull driver and its associated receiver connected by a transmission line. To simplify even further this setup, we can replace the receiver by its input capacitance. We can also add parallel terminations to mimic the ODT behaviour.

               

              In the case when the ODT is off and the input stimulus is logic low the current will flow from the transmitter’s power supply pin through the pull-up transistor, TL and it will charge the input capacitance of the receiver (the push-pull driver is an inverter). When the input stimulus changes its value to logic high, the pull-up transistor is turned off while the pull-down transistor is turned on. The input capacitance of the receiver is now discharged through TL and the impedance of the pull-down transistor. The two transistors might be on at the same time for a small period of time and that will give rise to an unwanted current that flows from the power supply pin directly to the ground pin. This current is called crow-bar current. Typically this configuration is called voltage mode.

               

              If the ODT is on, then the pull-up current will flow from the driver’s power pin through the pull-up transistor, TL and pull-down resistor to ground. The pull-down current will have an opposite direction and will flow from the receiver’s power supply through the pull-up termination resistor, TL and pull-down transmitter transistor to the transmitter ground pin. The shape of the pull-up and pull-down currents will be different depending if the stimulus contains transition or non-transition bits. There will be return current that will flow through reference planes even before the signal reaches the load, due capacitive coupling between TL and its reference planes. The high-speed current flow will follow the signal trace due to proximity effect. Typically this configuration is called current mode.

               

              For differential signals the story is slightly different since there is no net current change from power supply. This is why we do not worry about SSN in differential systems.

              I have attached for you a very simple LineSim setup along with corresponding models that will allow you to visualize the signal and power/ground currents for a single ended DDR3 DQ line. You will need Hspice to be able to run the simulations. The setup can be modified to make it work in ELDO as well. You can toggle between oscillator and PRBS stimulus by editing (comment out) the stimulus file. The top topology uses an ideal power supply, while the bottom topology contains an S-parameter model extracted from PDN. You can add/remove more details to this setup at your wish. I have also attached a screenshot of the waveforms that show the signals and power/ground currents for the two cases ideal vs. non-ideal PDN.

               

              If you go to at the link below you will find lots of good documents explaining in detail the SI/PI co-simulation process, modeling techniques and the industry trend:

               

              http://www.eda-stds.org/ibis/summits/index-bydate.htm

               

              For additional details about LineSim usage applied to this type of simulations, you can have a look at Mentor’s AppNote 10839.

               

              Hope this helps.

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              • 4. Re: Hyperlynx Plane  Noise Simulation
                rpotluri

                Hello Filip,

                 

                I thank you very much for your model. I was trying to simulate in your model to understand the concept you explained here but it results in an error. Could you help me out with that please.

                 

                Thanks and Regards,

                Ravi

                • 5. Re: Hyperlynx Plane  Noise Simulation
                  cristian.filip

                  Hi Ravi,

                   

                  The simulation deck that I have provided runs without errors if you use HSpice instead of ELDO/ADMS as Spice engine. If you don’t have HSpice you will have to do several modifications in order to make it work with ELDO and perhaps Mentor folks are better positioned to help. Few differences that I am aware of are:

                   

                  • IBIS element in ELDO is specified with the “_IO_” prefix, while in HSpice the I/O buffer is referred as B-element and is called using the “B_IO” prefix

                  • HSpice does support Voltage Controlled Capacitances (VCCAPs) that I am using on my Memory Controller model, to increase the accuracy of the simulations. I am not sure if ELDO does have a similar capability, so you might have to comment out or remove those capacitors

                  • The two Spice simulators are using different S-element syntaxes and statements for low frequency extrapolation (that are needed for the initial DC operating point calculation when using S-parameters). This means that you will need to modify my Spice wrapper for the S-parameter.


                  If you want to better understand the concept I would suggest you to read my U2U presentation from May 2012, Waltham, MA:

                   

                  http://s3.mentor.com.s3.amazonaws.com/supportnet/u2u/new-england-presentations/Filip_GeneralDynamics_pres.pdf

                   

                  I am also attaching a simple simulation deck that you can run with ELDO/ADMS and that might provide you a starting point in this area.

                   

                  Cheers,

                   

                  Cristian

                  • 6. Re: Hyperlynx Plane  Noise Simulation
                    rpotluri

                    Hello Cristian,


                    I thank you very much for your kind reply. I have gone through your slides and the program you gave and I really enjoyed them.


                    Best Regards,

                    Ravi

                    • 7. Hyperlynx Plane Noise Simulation (Postlayout Analysis)
                      rpotluri

                      Hello everyone,

                       

                      I am a student trying to learn PDN AC analysis in Hyperlynx. Could anyone of you kindly help me to do decoupling analysis for my application mentioned in the attached excelsheet?

                      Any examples or references or hints are highly appreciated. I thank you in anticipation.

                       

                      Best regards,

                      Ravi

                      • 8. Re: Hyperlynx Plane Noise Simulation (Postlayout Analysis)
                        cristian.filip

                        Hi Ravi,

                         

                        There is plenty of good documentation that you can use to improve your knowledge in the area of PDN analysis. I would suggest you here only few websites to visit:

                         

                        1. 1.      Istvan Novak’s home page

                         

                        http://www.electrical-integrity.com/

                         

                        Specifically for some of your questions you can read the sample chapter of the Power Distribution Design Methodologies book and you can download the Microsoft Excel demo file that calculates the frequency – domain response of single and multiple bypass capacitors that you can find under the tool download area..

                         

                        http://www.electrical-integrity.com/PDNDesignMethodologies_files/PDN_DesignMethodologies_Chapter-5.pdf

                         

                        1. 2.      Dr. Eric Bogatin’s book: “ Signal and Power Integrity – Simplified” and hands on labs and presentations

                         

                        http://www.bethesignal.net/bogatin/hol134-simple-analysis-p-767.html?cPath=25

                         

                        1. 3.      Lee Ritchey’s “Right the First Time” book (Volume 1 and 2)


                                      http://www.speedingedge.com/index.htm

                                       http://www.thehighspeeddesignbook.com/

                         

                        1. 4.      Sigrity - technical papers

                         

                        http://www.sigrity.com/success/techpapers/support_tech_doc.htm

                         

                        1. 5.      EMC Society Eastern North Carolina Chapter


                                       http://ewh.ieee.org/r3/enc/emcs/presentation_archive.htm

                                       http://ewh.ieee.org/r3/enc/emcs/archive/2012-10-10b_DecouplingMyths.pdf

                                       http://ewh.ieee.org/r3/enc/emcs/archive/2012-09-04-DL-Talk_1_Schuster.pdf

                                       http://ewh.ieee.org/r3/enc/emcs/archive/2008-04-01-Application-of-X2Y-Capacitors.pdf

                         

                        1. 6.      Sun Microsystems paper “Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology”


                                          http://www.si-list.net/files/published/sun/cpmt_1999.pdf

                         

                        I hope this helps,

                         

                        Cristian

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                        • 9. Re: Hyperlynx Plane Noise Simulation (Postlayout Analysis)
                          potluri.ravikumar

                          Hi Cristian,

                           

                          Thank you very much for your suggestions and resources. I think I have got a nice entry point.

                           

                          Best Regards,

                          Ravi

                          • 10. Re: Hyperlynx Plane Noise Simulation (Postlayout Analysis)
                            rpotluri

                            Hallo Everyone and Cristian,

                             

                            Could you also please give some suggestions to the following problem. How to model for Analog rails in Hyperlynx? Please find the attached screenshot of the situation.

                            Here, we have ferrite beeds between the source and load. How to do decoupling analysis with a ferrite beed. Any example would be highly appriciated.

                            Thank you very much in advance.

                             

                            Best Regards,

                            Ravi

                            • 11. Re: Hyperlynx Plane Noise Simulation (Postlayout Analysis)
                              yu.yanfeng

                              Ravi,

                              If you are interest see the total effect of your filter network, just create a subckt model for the fiter circuit, and assign this model  one of capacitor , which connected to the power. However, the tool is targeted to Power plane analysis, fanout'effect. For power filter circuit analysis, you may need Hyerplynx analog.

                               

                              The practical way to analye the performance from VRM to the load point  in Hyperlyn is that you first export a PDN model, and re-create total topology in Linesim.

                               

                              Yanfeng

                              • 12. Re: Hyperlynx Plane Noise Simulation (Postlayout Analysis)
                                potluri.ravikumar

                                Hello Yanfeng,

                                 

                                Thankyou very much for your kind reply. I understand that you recommend me to model the filter network as RLC and assign that model to a capacitor which is connected in series to the VRM?.

                                As I am newbie to the Hyperlynx simulations I would be very glad to see an example where one creates the total topolgy of an exported PDN model (Simple model). I think method gives the designer more degrees of freedom to analye the PDN.

                                 

                                Best Regards,

                                Ravi

                                • 13. Re: Hyperlynx Plane Noise Simulation (Postlayout Analysis)
                                  rpotluri

                                  Hello Yanfeng,

                                   

                                  Thankyou once again for your inputs. I would like to share the solution over here.

                                   

                                  Best Regards,

                                  Ravi

                                   

                                  http://supportnet.mentor.com/reference/technotes/public/technote.cfm?id=MG502177

                                  • 14. Re: Hyperlynx Plane  Noise Simulation
                                    rpotluri

                                    Hello Cristian,

                                     

                                    Could you please explain me how to extract S-Parameter (S2P) model from PDN as in your above example (Test_case)?.

                                    Why did you use voltage source "V 3 2 0.2314V" in SPICE_WR.sp file to load S-Parameters file?

                                     

                                     

                                    Thanks and Regards,

                                    Ravi

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