i'm interested in simulating a DDR interface for Non-JEDEC Standard, based on PLL only topology.
My system involves a PPC440EPX and four MT47H16M16BG-37E memory chips. The configuration doesn't have any register for Cmd/Add/Ctrl and the clock signal from the controller is distributed through a PLL to the SDRAMs.
The assigning model issues are fixed (after some time spent reading IBIS 4.0) and i have already done succesful simulations with the DDRx wizard, following HyperLynx's help suggestions for data lines.
However, i dont know how to perform CLK to DQS Skew measurements, which are even more interesting than those regarding Data lines.
If someone could give me any clue, would be great...Does anybody have any suggestion of how could i proceed ?
I look forward to your comments
Best regards ...!