5 Replies Latest reply on May 17, 2012 12:18 PM by cristian.filip

    DDRx Wizard Simulation Setup for PLL Only Topology (Hyperlynx 8.1)

    gracia.lorenzo.garrido

      Hello everybody...!

       

      i'm interested in simulating a DDR interface for Non-JEDEC Standard, based on PLL only topology.

      My system involves a PPC440EPX and four MT47H16M16BG-37E memory chips. The configuration doesn't have any register for Cmd/Add/Ctrl and the clock signal from the controller is distributed through a PLL to the SDRAMs.

       

      The assigning model issues are fixed (after some time spent reading IBIS 4.0) and i have already done succesful simulations with the DDRx wizard, following HyperLynx's help suggestions for data lines.

      However, i dont know how to perform CLK to DQS Skew measurements, which are even more interesting than those regarding Data lines.

       

      If someone could give me any clue, would be great...Does anybody have any suggestion of how could i proceed ?

      I look forward to your comments

       

      Best regards ...!

        • 1. Re: DDRx Wizard Simulation Setup for PLL Only Topology (Hyperlynx 8.1)
          cristian.filip

          If your Clock PLL and the Memory Controller are on the same board you might be successful to simulate by using the DDRClkWizard.exe application that you can find under the HyperLynx installation directory. I have had to simulate a similar topology but with memory chips on SODIMM and I have learned that it was not supported in HL. Consequently I have submitted an enhancement request through the Mentor’s Ideas website (D3810 – Jan 6, 2011).

          • 2. Re: DDRx Wizard Simulation Setup for PLL Only Topology (Hyperlynx 8.1)
            gracia.lorenzo.garrido

            Hi Cristian,

            Thanks so much for your help (...sorry for delayed reply)

             

            Both ICs (Controller and PLL) are on the same board. SO i tried what you told me with the DDRClkWizard.exe and everything seems to work fine (merging IBIS and saving new HYP file).

            However I have a couple of questions regarding how to perform the analysis after doing this:

            • I guess that the resulting hyp file internally re-connects lines between PLL and PPC, resulting a unique chip, am i right?
              If so, should I specify "unbuffered" into the configuration stage from the DDRx wizard with the new merged hyp file?
            • And secondly: The DDRClkWizard.exe says that i have to "manually create a timing model file to account for the additional timing ambiguities in the clock path caused by the buffer and the controller-to-buffer clock interconnect". I guess I can take the PLL time from DS but, how can i get the controller-to-buffer clock interconnect time, in order to create the timming model?
              Should i measure it with HL ?

             

            Thanks again for your comments.

            I look forward to your suggestions.

            • 3. Re: DDRx Wizard Simulation Setup for PLL Only Topology (Hyperlynx 8.1)
              weston_beal

              Your assumption that the utility creates one merges IC is pretty much correct. Now you have one logical IC for the controller, so the bus behaves like an unbuffered bus.

               

              The timing model now needs to take into account the possible skew between the clock from the original clock output of the controller and the clock outputs of the PLL. Since the timing model of the controller has most quantities referenced to the clock, all these quantities now need to include the possible skew between the signals and the clocks out of the PLL. Evaluate the routing (HL batch simulation timing) from the controller to the PLL, the skew tolerance of the PLL, and the feedback loop that controls the PLL phase shift. Add these all together to get the total min and max skew created by the PLL, and include these times into the quantities in your timing model that have anything to do with the controller clock.

               

              May the force be with you :)X You will need it.

               

              Weston

              • 4. Re: DDRx Wizard Simulation Setup for PLL Only Topology (Hyperlynx 8.1)
                gracia.lorenzo.garrido

                Hi Weston,

                First of all, thanks for your reply.

                 

                Oh my God....I have to say that i never thought performing signal integrity analysis would involve mastering on Jedi arts....:-(.

                Nevertheless, i'm going to do my best and i'll try to achieve a coherent timing model file...

                 

                It would be helpful keeping your support...I'll let you know the results and/or trouble.

                 

                A deeply grateful padawan.

                • 5. Re: DDRx Wizard Simulation Setup for PLL Only Topology (Hyperlynx 8.1)
                  cristian.filip

                  Regarding your comment about SI complexity, most of the SI evangelists are Ph.D.s… If it was so easy, SI would have been taught in high-school.