HyperLynx DRC is a new Mentor product currently in Beta that is about to release. HyperLynx DRC has a number of built-in design rule checks targeted at pinpointing possible EMI issues, as well as Signal Integrity and Power Integrity issues.
The design rule check you referenced below is the I/O Coupling DRC, which checks for excessive coupling of high-speed traces to I/O nets. Coupling between these two types of nets creates a risk of high-frequency noise leaving the system through the I/O net. Most I/O signals (signals that go "outside the box") are slower signals and do not pose as much of a radiation risk, but if higher-frequency energy couples onto these nets they become a much larger radiation risk.
A great example of the relevance of this rule is when testing a device in an EMC chamber that passes until you plug the cables into it, and then it starts failing.
In regards to the addition of trace segment lengths (D1 and D3), this is done because every closely-coupled segment couples more high-frequency energy onto the I/O net. You are correct that it is probably best to run a crosstalk simulation to find the exact coupling of all sections, and we encourage our users to use simulation data to create these rules. The beauty of HyperLynx DRC is that it is highly customizable. You can customize the built-in rules using several built-in parameters, or you can write your own rules for anything you can imagine. Susceptibility is a good candidate for such a rule.
Our customers range from novices to very advanced users. The novices, who may not know exactly what to simulate, like HyperLynx DRC because it provides a nice comprehensive list of checks for their board. The more advanced users like the ability to customize it to write any rule they want. A common use is to check for EMI issues - issues that cannot be practically simulated on a system level but that still need to be addressed, like broken return paths.
As Paul pointed out, there are many manual checks that a user will perform on a board during a design review, and these checks can be automated using HyperLynx DRC.
In regards to pricing, we do have many different packages for all our tools with different levels of pricing, let's make sure you have the latest info. The best way to do that would be contacting your account manager directly (if you don't know who that is, I'll be happy to send your his info in a private message).
Thanks for taking the time to respond.
I have to admit my question was somewhat of a "fishing expedition"... I don't mind showing my ignorance if I can learn something from it.
What I learned so far is that the SI-List isn't really interested in discussing this type of tool, and so far I can't find any group here or anywhere else that is talking about having QE incorporated into their design process. If you search the entire Mentor Community for "QuietExpert" or "Quiet Expert" you will get a few hits, but absolutely NOTHING relevant.
Don't get me wrong, I am willing to invest the time to learn a new tool, and this may be something we can really use, but I was hoping to get a "warm fuzzy" about it from actual users before I dive in.
and sorry if I stepped on any toes,
Jack (aka "the new guy")
While HyperLynx DRC is similar to Quiet Expert in that it checks design for potential electrical issues, there are a lot of differences (most of them centered around the reasons you don't see a lot of posts on QE). . I won't go into the details here, but maybe we should get a call setup for you so we can talk through those details and answer any questions you have.
Since HyperLynx DRC isn't actually released yet, you won't see much about it anywhere. We are running a beta program currently and about to release and I can say that there is interest in the tool outside of you taking a look :-).
We are using QE for years and I have joined the Hyperlynx DRC beta program. It can help user to audit design's compliance to corp rules for EMC/EMI rules after investing resources to write customized rules. QE rules are TCL based, but Hyperlynx DRC aodpot the Automation Object Model make it more ease to write customized rules. However, it still need you have better knowdges about programming for some cusotmized rules. I hope Hyperlynx DRC
A. support check schematics (based on CCZ data and ibis model etc to capture following common errors which design entry isn't able to capture
1) capacitors's polarity connection error, insufficent rated voltage etc
2) differ pair's polarity connection error
3) bus bit assignment error
4) Decup's strategy
5) net name labing check
B. further easy the programming for customized rules. most of hw engineer don't having time to learn details about object model.
C use VisECAD OCX as layout viewer and write checking result wich can be read by VisECAD viewer.