DDRx Simulation in Hyperlynx 8.2

Discussion created by jose.fundora on May 17, 2012
Latest reply on Jul 16, 2013 by pjrajda

Dear Expert,


I have run simulations for the FPGA I am using with a Micron DDR3 memory.  Looking at the results is there a way to have the simulator look at the waveforms at the die instead of at the pin?  It would be less time consuming checking to see if for example my DQ lines failed the Vref multicross and when I look at the waveforms it looks good at the die, but does fail and look bad when at the pin.  Let me know if there is anything that can be done about this or if I have to double check the sim results to see if it actually failed or not.