LVS comparison doesn't always depend on power and ground nets to be identified. It's usually helpful but not strictly always required. In your current case it seems that LVS comparison can be successful because there is enough information to find a match between source and layout. The comparison step is different from the PATHCHK though... The errors you mentioned about no power nets being found relate only to PATHCHK. It seems the LVS run that you are doing, has some ERC checking activated, and those messages warn that those checks are being skipped because there isn't enough net labeling information to proceed with the check.
To decide if you should label the pads, it would be important to decide a few things. If you really have circuitry that you want to be checked for ERC style pathchk, then you probably need to label all the power and ground pads. If you want to check to make sure that the internal circuitry connects all the way to the pads, then you probably will want to label all the pads, not just the power and ground. To decide which layer to use for pad naming, you will need to use a layer that is used for connectivity in the rule file, and also that has TEXT LAYER statements associated with it, and maybe also ATTACH statements to make sure it connects to the proper layer if the text layer and the connectivity layer are different.