7 Replies Latest reply on Jun 14, 2012 6:06 AM by cristian.filip

    Unexplainable warning in DDRx Batch Simulation

    erdin.sinanovic

      Hello!

       

      I want to run a DDRx simulation. I have everything set up, but I get a strange error and I can't explain why. Here's the logfile:

       

      Software Version: v8.1 build 511 (511, 0)

       

      ** WARNING ** : U2.L2 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.B9 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.M8 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.D10 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.M2 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.C8 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.N8 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.A8 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.M3 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.C7 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.H7 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.A12 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.M7 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.A7 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.N2 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.A6 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.G1 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.A15 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.H3 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.C11 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.H2 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.C12 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.G9 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.C14 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.J2 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.A11 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.K8 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.D12 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.J3 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.A10 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.K3 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.A9 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.L7 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.B12 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.L3 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.C9 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.K2 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.C10 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.L8 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.D11 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.F3 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.D14 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.G3 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.D13 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.K7 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.C13 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U2.N3 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      ** WARNING ** : U1.B6 pin of DDR3_CKP net does not have opposite pin although net is supposed to be differential

      NETS FOR AUDIT

      **********************************************************************

      Nets Selected For Simulation (3):

      DDR3_CKP, DDR3_DQSP, DDR3_DQ6

       

      NEXT RUN INFORMATION

      **********************************************************************

      Audit for the net: DDR3_CKP with type: W1_Typ

      ** Error **: Too many drivers, not allowed in the DDR interface! Driving pins: U1.A14, U1.B9, U1.D10, U1.C8, U1.A8, U1.C7, U1.A12, U1.A7, U1.A6, U1.A15, U1.C11, U1.C12, U1.C14, U1.A11, U1.D12, U1.A10, U1.A9, U1.B12, U1.C9, U1.C10, U1.D11, U1.D14, U1.D13, U1.C13, U1.B6

      ** Info **: Initialization of drivers failed!

        

      NEXT RUN INFORMATION

      **********************************************************************

      Audit for the net: DDR3_DQSP with type: W1_Typ

      NEXT RUN INFORMATION

      **********************************************************************

      Audit for the net: DDR3_DQSP with type: R(1,1)_Typ

      NEXT RUN INFORMATION

      **********************************************************************

      Audit for the net: DDR3_DQ6 with type: W1_Typ

      NEXT RUN INFORMATION

      **********************************************************************

      Audit for the net: DDR3_DQ6 with type: R(1,1)_Typ

       

      AUDITOR ERRORS REPORT

      **********************************************************************

      Net DDR3_CKP:

      Too many drivers, not allowed in the DDR interface! Driving pins: U1.A14, U1.B9, U1.D10, U1.C8, U1.A8, U1.C7, U1.A12, U1.A7, U1.A6, U1.A15, U1.C11, U1.C12, U1.C14, U1.A11, U1.D12, U1.A10, U1.A9, U1.B12, U1.C9, U1.C10, U1.D11, U1.D14, U1.D13, U1.C13, U1.B6

      Net DDR3_DQSP:

      No errors;

      Net DDR3_DQ6:

      No errors;

      END TIME

      **********************************************************************

      Date .............................Jun.-13-2012

      Time .............................11h-18m

      Total Run Time ................... 0 Days, 00 Hours, 00 Minutes 09 Seconds

       

      **********************************************************************

       

       

      The pins, which the warnings are referencing to, are the control pins of the controller and the DRAM module. The error at the bottom seems to be connected to the warnings from above...

      Can someone shed light on this issue?

       

      Cheers!

        • 1. Re: Unexplainable warning in DDRx Batch Simulation
          cristian.filip

          It seems that the issue is coming from your clock net (DDR3_CKP). Accordingly to the content of the log file it appears that there are only two ICs connected to this net (U1 and U2) with many pins attached to it at both ends. Clocks and strobes are supposed to be differential, but in your simulation only the *P net shows up. I would suggest selecting the DDR3_CKP and DDR3_DQSP nets and inspect them visually in BoardSim. Open the “Assign Models” menu and look at the content of the “Pins” column. Check your models pin out and make sure that you have properly defined the power and ground nets. Finaly try to simulate those nets interactively in BoardSim prior to lunch the DDRx Wizard.

          • 2. Re: Unexplainable warning in DDRx Batch Simulation
            erdin.sinanovic

            I have defined the clock as well as the DQS nets as differential in the IBIS file of both ICs. The other nets are not connected to the clock net. The "Assign Models" window seems to be ok... I have assigned the IBIS files to the ICs by reference, so all the pins show up correctly. Do I have to configure the differential pins in Hyperlynx itself or is the definition in the IBIS file sufficient?

            • 3. Re: Unexplainable warning in DDRx Batch Simulation
              cristian.filip

              The IBIS file definition for differential pins should be sufficient, but it doesn’t hurt to identify the diff pairs in HL as well. However that won’t solve your issue. Again, check your power nets assignment and try to simulate interactively your clk and strobe nets. Maybe you should open an SR at Mentor if that works, and have the AEs helping you.

              • 4. Re: Unexplainable warning in DDRx Batch Simulation
                cristian.filip

                Something doesn’t make sense in your messages. You said: “The pins, which the warnings are referencing to, are the control pins of the controller and the DRAM module.”From this sentence I would assume that there is a Memory Controller (say U1) and a DIMM or SODIMM in your setup. In this case I would expect to see only two clk pins connected to your MIC (U1) and a couple of memory chips connected at the other end, which doesn’t seem to be the case accordingly to the content of your log file.

                • 5. Re: Unexplainable warning in DDRx Batch Simulation
                  erdin.sinanovic

                  Yes you read right, and for me it doesn't make sense either. All the warnings are referencing to the control pins of the memory interface (i.e. A0-A13, BA0-BA2, RASN, CASN, CSN, CKEN, ODT, RESETN, whereas U1 is the uC and U2 is the DRAM chip). The warnings imply, that these nets are connected to the clk net, which is not correct or at least they shouldn't be connected to the clock net. I don't have a netlist or the design data to crosscheck the connections... just the HyperLynx project. From HyperLynx the design looks ok (no shorts). How do I check whether power and ground are defined properly?

                  • 6. Re: Unexplainable warning in DDRx Batch Simulation
                    erdin.sinanovic

                    I've found the cause!

                    It was a missing power net definition. I've contacted the designer of the PCB and he gave me the information, that I should add this specific net to the power nets. Now it's running flawlessly. Thanks for your help!

                    • 7. Re: Unexplainable warning in DDRx Batch Simulation
                      cristian.filip

                      I’m glad I could help. Good luck with your simulations!