jose.fundora

DDR3 Diff Signals

Discussion created by jose.fundora on Jun 14, 2012
Latest reply on Jun 14, 2012 by weston_beal

I have two pairs of differential signals going to a DDR3 chip.  When reading or writing one of the signals passes and the other fails.  These signals are matched to the length of their signals and to each other.  Meaning Diff pair 1 have matched lengths to signals such as DQ[7:0] and the other to DQ[15:8].  As you can see below the failing diff signal is very clean.  Is Hyperlynx saying this signal is failing due to the crossover not being lower?  The difference in starting rise/fall time for the failing signal is ~20ps.  The difference in starting rise/fall time for the passing signal is ~12ps.  Any help would be greatly appreciated.  Thanks!

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