3 Replies Latest reply on Jun 14, 2012 11:40 AM by weston_beal

    DDR3 Diff Signals


      I have two pairs of differential signals going to a DDR3 chip.  When reading or writing one of the signals passes and the other fails.  These signals are matched to the length of their signals and to each other.  Meaning Diff pair 1 have matched lengths to signals such as DQ[7:0] and the other to DQ[15:8].  As you can see below the failing diff signal is very clean.  Is Hyperlynx saying this signal is failing due to the crossover not being lower?  The difference in starting rise/fall time for the failing signal is ~20ps.  The difference in starting rise/fall time for the passing signal is ~12ps.  Any help would be greatly appreciated.  Thanks!

        • 1. Re: DDR3 Diff Signals

          There are multiple failure mechanisms. Did the failure appear in the SI results or in the timing margin results spreadsheet? Because you focused on the crossing point voltage, I assume that the report specified this as the failure. Is that correct?


          The timing offset of the rising and falling edges usually cause this type of error, but the measurement is actually at the voltage where the rising and falling edges cross. The range for the crossing point voltage is specified in the receiver IBIS model [Receiver Thresholds] section. Unfortunately, the oscilloscope window does not show these thresholds. You have look in the IBIS file and then compare the waveform measurement to the values in the IBIS file.

          • 2. Re: DDR3 Diff Signals

            The failing was on the SI measurements.  The crossing point was the only thing that could be wrong.  The signal looks fine to me.  I will check what the values are in the Receiver Thresh and check to see what the crosspoint value is.  What would be the name of the parameter?  I will keep you posted as to what I find.  Thanks for all the help.

            • 3. Re: DDR3 Diff Signals

              The parameters in the IBIS file are Vcross_high and Vcross_low. If those parameters are not in the IBIS file, then the tool should use the JEDEC specified values. For DDR3, the cross point voltage is defined in section 8.4 of the specification, and are Vref (Vdd/2) +/- 150mV.