I was going thru app note 10706. You don't have to enter the setup and hold times for Address and control signals anywhere. Only the min and max (tckac, tckctl).
Does the timing wizard tool derive the setup/hold times from the min and max values?
The setup and hold time requirements are in the timing model of the receiver, which in this case is the DRAM.
Okay. So where do you enter the timing numbers for the receiver.
The app note only talks about controller timings.
There is a separate timing model file for the DRAM. Generally, you don't need to edit the default DRAM timing model. It is based on the JEDEC specification for DDR DRAM. Using the default DRAM timing model has the effect of testing your design to the JEDEC specification. On the other hand, JEDEC does not specify timing for the controller. Controllers might behave quite differently from each other. That is why it is a good idea to create a specific controller timing model. The appnote that you have helps you with this task.
Where to take the timings in DDRx Batch simulation TM Wizard,
From Controller Datasheet or DDR datasheet ?
Little bit confused after going through your manual,
Earlier i was taking it from DDR datasheet but
The DDRx Wizard requires two timing models, one for controller and one for memory chips. The controller datasheet provides the timing information needed to build the controller timing model while the SDRAM datasheet contains the timing details for the memory chips timing model. However the SDRAM timing is standardized (see the corresponding JEDEC document) so the default HyperLynx model should be fine for you. Memory controllers are different as the vendors have the freedom to implement various internal mechanisms, so you really need to create your own timing model and this is what the AppNote 10706 is all about.
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