I would like to check the decoupling caps for DDR2 interface. PCB has one split plane and one GND plane. On split plane there are several different power nets (including for DDR2).
Decoupling wizard is expecting a power/GND net to analyze its decoupling. If I define VDDQ power net as plane (for simulation) then track inductance is very low and results are misleading.
Can you suggest how to do decoupling simulation on power nets (without declaring it as power plane).