3 Replies Latest reply on Jul 6, 2012 11:35 AM by cristian.filip

    Probe Modeling




      Any suggestions on  how to model specific oscilloscope probes in Boardsim?  I am trying to get as accurate simulation results as possible, to match measured scope traces.

      Does the built-in oscilloscope model the probes and what values does it use? (10pf, 5pf probe etc)


      I know there is a probe.mod model library but I am not sure how to apply this?





        • 1. Re: Probe Modeling

          Spice is appricate for probe mdeling. You may need to look for the model from oscilloscope venders. Tek have a paper about the probe modeling for signal fidelity http://www.tek.com/technical-brief/tekconnect-probes-signal-fidelity-issues-and-modeling.




          For accurate result, the key is the driver/recerver model, or  via modeling if GHz bit rates.  It seems no worthful to put effors on the probe modeling except you are reasching how to design a probe with high signal fidelity.


          • 2. Re: Probe Modeling

            Maybe a better idea would be to de-embed the effect of the probes on your lab measurements and correlate those measurements with your simulations. At the end of the day what matters is the quality of signals that the chips on the board will see and not what the oscilloscope measures…



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            • 3. Re: Probe Modeling

              While trying to correlate simulated vs. measured waveforms you should be aware of all the limitations of both methods. Here are some examples.




              Ideal planes

              ·         Ideal power supply

              ·         Effects of stitching vias and bypassing capacitors not accounted for

              ·         Wrong estimated jitter contribution

              ·         Missing package parasitic information or package level crosstalk ignored




              ·         Probe parasitic

              ·         Inductance of the grounding connection

              ·         Difficult to probe at the right location

              ·         Driver strength unknown

              ·         PCB impedance variation unknown (need to perform TDR measurements)

              ·         Long measurement time to acquire enough bits for a meaningful eye diagram (SerDes)

              ·         Impossible to probe large parallel buses (DDR)

              ·         Sometimes difficult to generate the right test pattern


              If you look at those factors and some others you’ll figure out that it is difficult to compare apples to apples and the probe parasitic is just one element out of many that might be responsible for mismatch.