7 Replies Latest reply on Jul 11, 2012 3:10 AM by matthias.cosaert

    DDR3 clk simulation waveform issue

    kzhang

      Hi There, 

       

      I am using Hyperlynx to run the DDR3 675MHz clock simulation on our PCB layout, the simulation waveform looks weird.  Basically we are using the 32 Bit memory controller connect to 2 16bit DDR3 memory part, the topology is T branch without Vtt termination at far end memory side. When I ran the simulation on the far end memory side, the waveforms show really strange, the first period of simulated clk looks fine, but it become worse cycle by cycle, and you will see the final cycle show a lots of overshoot/undershoot, it looks like infinite resonance on the signal. I don't really believe it is the really case if we measure the clock at the same point. I suspect something might be wrong in the Hyperlynx.  We do not make the real board yet, so i could not really measure it at this point to confirm it.

       

      Please see the attached snapshots to show the issue i described above, let me know you saw this before or you have any idea. Appreicated!

       

      Cheers,

      Kai, LG_USB_Rev_B1_0pf_22_Ohm_CK_675MHz_Typ_(at_Die).JPG

      LG_USB_Rev_B1_0pf_22_Ohm_CK_675MHz_Typ_(at_Pin).JPGLG_USB_Rev_B1_2_2pf_22_Ohm_CK_675MHz_Typ_(at_Die).JPGLG_USB_Rev_B1_2_2pf_22_Ohm_CK_675MHz_Typ_(at_Pin).JPG

        • 1. Re: DDR3 clk simulation waveform issue
          Ed Bartlett

          Hello Kai,

                      It appears that the series capacitors are not charged up fully. I would run the simulation for a very long time and check for the expected DC levels at the loads.

          Best regards,

          Ed.

          • 2. Re: DDR3 clk simulation waveform issue
            kzhang

            Thanks Ed. one more experiments. If we change the DDR3 clock to 750MHz or 800MHz, we did not really see the simulation waveform become worse cycle by cycle. We used the fly-by topology on the DDR3 before, and I never saw this kind of issue, the clk waveform looks almost identical on every single cycle. Now we changed the design back to T-branch and removed the Vtt termination for cost saving purpose, the waveform looks relative fine at first cycle, but I become worse cycle by cycle, and finally go crazy and completely out of DDR3 spec requirement. What do you mean by series caps? can you elaborate it?

             

            CLK signal interconnect:  

            Memory controller drive differential CK/CK# out -> 22ohm serial resistor on CK/CK# (we also added the 2.2pF cap cross the CK and CK# as option) -> T-branch -> 2 16bit DDR3 parts

             

            Cheers, kai

            • 3. Re: DDR3 clk simulation waveform issue
              Ed Bartlett

              Hello Kai,

                   That is good information on the additional experiment. When I saw the waveforms on your first posting and saw in the scope the probe points at C27 and C138 it appeared to me that the circuit had capacitors charging up because the waveforms were growing in magnitude cycle to cycle. HyperLynx starts out the simulation with capacitors discharged. If you are seeing issues only at a certain frequency it would be good to open a service request and have one of the support engineers look at the circuit closely to find root cause for the issue.

              Best regards,

              Ed.

              • 4. Re: DDR3 clk simulation waveform issue
                kzhang

                Hi Ed, How can I open the service request?  Do I need to fill other ticket for the issue? Cheers,  Kai,

                • 5. Re: DDR3 clk simulation waveform issue
                  Ed Bartlett

                  Hello Kai,

                       To open a service request, log in to supportnet http://supportnet.mentor.com/  then click the  "service request" tab. The open a new service request page will appear. Select product HyperLynx SI/PI, and then add the description of the issue and follow the prompts to open a new service request.

                  Best regards,

                  Ed.

                  • 6. Re: DDR3 clk simulation waveform issue
                    kzhang

                    Thanks a lot Ed. I will do it.

                    Cheers, kai

                    • 7. Re: DDR3 clk simulation waveform issue
                      matthias.cosaert

                      Try exporting an S-parameter model (If you the licence) for the transmission line from the controller to one of the DDR3's to see the behavior in the frequency domain. (might be a resonance peak at that specific frequency for S11)

                      In the touchstone viewer you can change to differential mode with convert -> mode -> Standard to differential

                       

                      Can also check the reflections by only simulating a rising/falling edge. (now the driver toggles the output before the reflections arrive back to the driver)

                      Also make sure lossy line simulation is enabled.

                       

                      Adding an 100Ohm termination resistor between CK and CK# should reduce most reflections.

                      Should simulate to check the best position though (100 Ohm at branch or 200 Ohm at each DDR3)