kzhang

DDR3 clk simulation waveform issue

Discussion created by kzhang on Jul 10, 2012
Latest reply on Jul 11, 2012 by matthias.cosaert

Hi There, 

 

I am using Hyperlynx to run the DDR3 675MHz clock simulation on our PCB layout, the simulation waveform looks weird.  Basically we are using the 32 Bit memory controller connect to 2 16bit DDR3 memory part, the topology is T branch without Vtt termination at far end memory side. When I ran the simulation on the far end memory side, the waveforms show really strange, the first period of simulated clk looks fine, but it become worse cycle by cycle, and you will see the final cycle show a lots of overshoot/undershoot, it looks like infinite resonance on the signal. I don't really believe it is the really case if we measure the clock at the same point. I suspect something might be wrong in the Hyperlynx.  We do not make the real board yet, so i could not really measure it at this point to confirm it.

 

Please see the attached snapshots to show the issue i described above, let me know you saw this before or you have any idea. Appreicated!

 

Cheers,

Kai, LG_USB_Rev_B1_0pf_22_Ohm_CK_675MHz_Typ_(at_Die).JPG

LG_USB_Rev_B1_0pf_22_Ohm_CK_675MHz_Typ_(at_Pin).JPGLG_USB_Rev_B1_2_2pf_22_Ohm_CK_675MHz_Typ_(at_Die).JPGLG_USB_Rev_B1_2_2pf_22_Ohm_CK_675MHz_Typ_(at_Pin).JPG

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