This depends on how your vendors’ datasheets define the AC timing constraints. Usually it is at the die and package lengths (parasitics) have to be accounted for in both simulation and PCB routing rules since package parasitic is responsible for additional delay and waveform signal quality degradation.
I already look at that in the datasheet, but i don't find this information.
Do you know what have i to do with an ALTERA ?
The simulation can be considered for "worst case" compared to "always @pin" if probed @die,since the pin parasitics will be taken in account.
If the model of the reciever does not define the pin characterstics,the tool will take predefined parasitics values.
As far as ALTERA FPGA is concerned,the one that am using has the R-L-C values of the pin in the model.
Mostly for altera it will be given in model.