1 2 First Previous 24 Replies Latest reply on Aug 9, 2012 11:51 AM by cristian.filip

    Plane Noise, Z profile a discrepancy that I can't understand

    oscar.martinelli

      Dead All,

      Working with linesim I have designed a very simple pds that include a couple of plane, a vrm, a C, and one IC PIN. Very easily I have extract the z profile up to 100Mhz in the IC pin area.

       

      Then I have tried to run the plane noise simulation after have applied a sinusoidal stimulus to the IC pin.

       

      My question is: why I am not able to get the same voltage noise value from the two analisys?

      Example:

      1. From decoupling analisys at 20Mhz, Z=0.1 ohm if I=0.5A V ripple would be 50mV

      2. From voltage noise tool giving to the IC pin a sinusoidal stimulus IMAX=0.5A freq.=20Mhz the max ripple measured on the IC area is alway considerably smaller =28 mV.

       

      Many thanks

      Oscar

        • 1. Re: Plane Noise, Z profile a discrepancy that I can't understand
          Steve_McKinney

          Hi Oscar,

           

          I replied to your post on the si-list but I'll copy my reply here for other that are watching the community and would like to know about this:

           

          Based on what I think you are trying to do (correlation to some measured results), I would use a current stimulus with an edge instead of the sinusoid.  Specifying an edge will give you more control over the frequency content in the current waveform and represent the switching behavior of the IC better.  If you were trying to model power supply noise coming off your switching mode power supply, that's where you want to use the sinusoid.  

           

          -Steve

          • 2. Re: Plane Noise, Z profile a discrepancy that I can't understand
            cristian.filip

            Hi Steve,

             

            Regardless of the stimulus pattern Ohm’s low should apply. I guess that what Oscar can’t understand is why frequency domain and time domain simulations do not correlate.

             

            I have built a simple test case very similar to Oscar’s description that you will find in attachment along with my simulated waveforms (PI PowerScope and regular SI oscilloscope). In this particular example the magnitude of the self impedance at the IC pin is ~0.224 ohms (S-parameter value = 0.92) while the amplitude of the AC stimulus is 1A. Spice simulations using a sinusoidal current source show a noise with ~220mV amplitude, while PowerScope reports 404.8mV max noise voltage.

            I would be curious to figure out what I am doing wrong here, so the two simulations do not correlate at all. This is very important to be understood before performing more complex PI simulations.

             

            Thank you,

            Cristian

            • 3. Re: Plane Noise, Z profile a discrepancy that I can't understand
              cristian.filip

              Hi Steve,

               

              I did the experiment of replacing the sinusoid current source with trapezoidal current source and the discrepancy between PowerScope reported noise amplitude and Spice simulations is even larger: 0.3mV in PowerScope vs. 9.73V peak-to-peak in Oscilloscope. The stimulus used was the same: Pulse, 1A, init delay 0, rise time 0.2ns, fall time 0.2ns, trapezoid, pulse time 1ns, period 2.4ns, capacitance 0, resistance 1meg.

               

              Please see in attachment the new simulation deck along with simulated waveforms. Could you please comment? One special question is what is PowerScope measuring peak-to-peak value or RMS?

               

              Thank you,

              Cristian

              • 4. Re: Plane Noise, Z profile a discrepancy that I can't understand
                oscar.martinelli

                Hi Steave,

                i'm sending in attachment a document that describe how i did the mesuraments.

                 

                Regards,

                OSCAR

                • 5. Re: Plane Noise, Z profile a discrepancy that I can't understand
                  yu.yanfeng

                  I think I understand your question. In fact, Hyperlynx Plane Noise Analysis gives a consiste result which be same with Iac multipy Z@f(Z profile).  There are something you need to take care before to do comparison

                   

                  1) increasing sampling points during running decap analyzer.

                  2) shrink the reference pin distance to the IC's power

                   

                  Below is the snapshout  I did comparison on 100MHz, you will see plane noise is 726mv, the load I is 1A, 10ns(100MHz) sinusoidal. In Z profile, you will see z is 0.72762@ 100MHz, so V=1A  X 0.72762 ohm=726.7mv. I have checked it at 3M, 10M, 20M, 50M and 200MHz, all are same.

                   

                  I agree with Steve's comment for doing correlation between measurement and simulated results

                   

                  1.jpg

                  Yanfeng

                  • 6. Re: Plane Noise, Z profile a discrepancy that I can't understand
                    yu.yanfeng

                    Hi Cristian,

                    Hyperlynx measures peak-to-peak for noise only.

                    Yanfeng

                    • 7. Re: Plane Noise, Z profile a discrepancy that I can't understand
                      cristian.filip

                      Hi Yanfeng,

                       

                      I followed your suggestion about shrinking the reference pin distance to the IC’s power and I noticed very interesting results. For “Distance to Ref Pin” = 5 mils the noise voltage in PowerScope is reported to be 0.3mV. If I keep every other settings unchanged (1A, sinusoid, 100 Mhz) and reduce this distance to minimum allowed 0.394 mils, after re-running the simulation the noise increases to 2.3389V. That’s big change for a distance of 4.6 mils. Don’t you agree? See the compare screenshot below.

                       

                      I would like to hear Mentor’s comments on this topic.

                       

                      Cristian

                      • 8. Re: Plane Noise, Z profile a discrepancy that I can't understand
                        oscar.martinelli

                        Hi All,

                        i agree with Cristian, there is something wrong in my opinion.

                        I couldn't get the same results like Yanfeng, following his istructions.

                         

                        Thank All,

                        Oscar

                        • 9. Re: Plane Noise, Z profile a discrepancy that I can't understand
                          yu.yanfeng

                          hi,Cristian

                          I didn't check your test case, but I known Hyperylinx occasionally gives a strange results. To avoid this symptom, you have to close application or save design data and re-run it. Putting another 0.01u cap may be a workaround to this symptom~

                           

                          Mentor are resistant to discuss Hyperlynx's algorithm publically.

                          Yanfeng

                          • 10. Re: Plane Noise, Z profile a discrepancy that I can't understand
                            Steve_McKinney

                            Hi Guys,

                             

                            I was off performing my civic duty today in jury duty so I haven't had a chance to do anything today. I'll try to take a look in the morning.

                            • 11. Re: Plane Noise, Z profile a discrepancy that I can't understand
                              cristian.filip

                              Hi All,

                               

                              Beside those discrepancies between FD and TD, there is something else that I can’t understand when it comes down to the Plane-Noise simulations in TD.

                               

                              Assuming that we want to simulate a simple DDR3 DQ line toggling from logic low to logic high, (so on my previous setups we have U1.1 = VRM, U2.1 = memory controller and we can add somewhere else on the board U3.1 = memory chip) the current will flow from the U2.1 (power pin) through the pull-up MOSFET of U2, down the transmission line (DQ) and the pull-down resistor at U3 if the ODT is enabled. When switching from logic high to logic low, the current sense through TL will be reversed from the pull-up resistor at memory chip to the pull-down MOSFET at memory controller.

                               

                              In both cases, there is no current except the crowbar current that flows directly from U2.1 power to gnd pins. This crowbar current (leakage) is usually maintained very low by controlling the switching time of the pull-up and pull-down MOSFEs in the pre-drivers’ stages. Accordingly to the IC Power Pin(s) menu in the PDN Editor, all the current from the AC Power Pin Model stimulus flows from power to gnd (reference). Am I wrong? If so how to properly simulate the example described above using the Plane-Noise field solver?

                               

                              Thank you,

                              Cristian

                              • 12. Re: Plane Noise, Z profile a discrepancy that I can't understand
                                oscar.martinelli

                                Dear Steave,

                                have a had any chance to look into our queries about the correleation test?

                                 

                                At least, if there is any problem, would be usufull to know at the moment witch tools/analisys we can trust the most.

                                 

                                Kind Regards,

                                OSCAR

                                • 13. Re: Plane Noise, Z profile a discrepancy that I can't understand
                                  cristian.filip

                                  Hi All,

                                   

                                  There are a couple of other comments that should be made related to how the TD simulated noise could or not be correlated to lab measurements:

                                   

                                  • In any real board all the components including the ICs are mounted on a package, so at minimum there will be some series inductance and parallel capacitance (on die/package capacitance) with those ideal current sources that can be assigned as AC Power Pin Models into the IC Power Pins Editor

                                  • Those parasitic components will behave as low pass filters which will slower and roundup the stimulus’ edges. Consequently even for a trapezoidal stimulus (at the die power pin), the current that the power plane cavity will see will be almost a sinusoid (there might be some AM in top of it). This can be easily proved using my previous test case simulation decks and adding those missing components

                                  • The plane noise is highly dependent on the stimulus pattern. If we take again a DDR3 DQ line as example, the noise will be different (amplitude and spectrum) for a PRBS or an oscillator (periodic) type of pattern. Unless you have the full control over the data you are writing or reading into or from the memory, most of the real life traffic will look more as a PRBS stimulus. Usually the PRBS stimulus won’t provide the worst case noise since the signal spectrum is spread across a wide frequency band and it won’t excite power cavity resonances. However it should be noted that today there is no support in the TD PDN editor for a PRBS type of stimulus

                                   

                                  I would make few suggestions for enhancement of the PI tool in this area:

                                   

                                  ·         The easiest way to improve the accuracy of the tool would be to add the missing series and parallel parasitic into the Current Source model (can be something as simple as the advanced electrical model for VRMs). The customer would have the choice of using some default (average) values for those parasitics or if known use the actual values provided by IC vendors

                                  ·         More advanced improvements would allow using S-parameter or Spice models for the above parasitics

                                  ·         Finally the most complex implementation would allow the user to use a black-box on the Free-Form Schematic Editor for any driver/receiver. Then the IBIS element would be specified in ELDO using the prefix _IO_ while in HSpice using the B-element. The power pins could be exposed next through power =off/on Spice command and connected to the power plane cavity same way as we do it for IC’s or decoupling capacitors today. In other words the AC Models would be replaced by the actual current that flows through the IC power pins in SI simulations. This current would have the right dependency on the stimulus pattern and load. This implementation would be similar to Sigrity/Cadence’s tools while using Mentor’s existing algorithms. The stimulus pattern would be provided as input to the IBIS model into the Free-Form Schematic Editor and could be a simple Spice independent voltage source.

                                  ·         IBIS 5.0 support would also help

                                  ·         CPM models support might become something to looking into very soon

                                   

                                  Cheers,

                                   

                                  Cristian

                                  • 14. Re: Plane Noise, Z profile a discrepancy that I can't understand
                                    weston_beal

                                    I looked at this situation just a little bit and found that I can get good correlation between distributed decoupling and plane noise. In order to make them match, I changed a couple of options in the decoupling analysis wizard. First, select the Custom option, and then the options on the Custom Settings page are active. Disable Remove series inductance unique to each power pin and Enable stitching-via optimization. I did not change the grid size for FDTD (plane noise), but that might help. The point is to get HyperLynx to create the same circuit model in both cases. Then the math works out as expected.

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