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You may have heard about this "eqDRC" or "Equation Based DRC" business going around and may find yourself asking, "What exactly is this anyway?"

At first glance, you may think this is just marketing hype. Afterall, we've been able to use limited equations in DRC for some time. For example, in antenna checks, we look at the ratio of metal area to gate perimeters. In density we look at the ratios of areas of a layer inside of a window to the area of the window itself. May seem that this is old hat, right? The answer is "not really". Certain functions, like DENSITY and NET AREA RATIO do allow equations, but they only implement a very specific set of possible equations, specifically targeted to those applications. The concept of eqDRC is to enable more generic application of equations applied to various measurements for any kind of DRC or DFM.

Why is this suddenly needed? To put it simply, the kinds of issues that cause failures during manufacturing have gotten more complex. Historically, we could safely look at individual layers and measure their local spacings, widths and enclousres. Density and antenna checking covered the two major outlieing problems. But now, we have many lithography related impacts, chemical-mechanical polish impacts, and new electrical impacts. Checking a design for these kinds of problems generally involves looking at the interactions of multiple polygons, across many layers, for larger interacting regions. Checking these properly is practically impossible and those that can be done are expensive from a performance point of view, and very difficult to debug.

The typical example we like to show is width dependent spacing checks. Yes, these have existed in DRC for a few process nodes now. So, why would eqDRC be needed here? Quite simply because the current DRC approaches do not work! The typical approach is to identify polygons of various widths. Then you apply different spacing rules between the different sets or "buckets" of widths. While this gives a little more insight, it really doesn't help the designer understand the problem. The choice on the buckets hampers the accuracy of the rules, resulting in either over-constraining the design by forcing compliance to a rule that has no physical impact, or impacting yield by allowing compliance at a level where CMP failures will still arise.

Yes, you can address this. You could bucket every polygon on a layer to to buckets that are 1database unit apart. Then you can check every bucket to every other possible bucket, with a different spacing requirement. But, this is very expensive for performance and runtime. Its also a pain in the butt to code. Worse yet, it results in thousands of rules for one issue. The poor designer who gets a failure has no idea what to do to fix the problem!

That's where eqDRC comes in. We measure the widths. We measure the spacings. We plug the widths and spacings into an equation that simulates the CMP phenomenon. We find the violations. We also plug those results into an equation that can solve for the corret width if spacing is held constant, or solve for the correct spacing if the widths are held constant. With this, the designer has some guidelines on how to fix the problem!

This is just one example, probably the simplest to comprehend. What we've found is that at 45nm and below, the number of physical failure mechanisms that cannot be adequately captured in standard DRC is growing rapidly. Having eqDRC makes it possible to code these accurately and easily and allows a new mechanism to communicate the actual physical requirements for manufaturing to the designer. In other words, it brings the true ability to design for manufaturability!

Well, that's about as much detail as I can post into a simple blog. What questions do you all have?


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I just had a short look into the new feature of DRC Visualization . It's quite smart. DRC off now is much faster, you can really toggle. Then you route at those very dense areas, where no space is left. Immideately you see the DRC. (Ok, would be better you could set you own color an d pattern here) If you switch back to use the DRC you can repair it segment by segment :-) .
They really understood what we told them last year in Moscow. also new errors during this repair phase are possible and get marked. (Exactly what wee need)

Also the "repair selected" is very promising. I deleted a signal in a complete bus over 30cm lenght. Then I added it again where it was, but got all with errors, because as all of you know, it does not find the center, where no error is. I hoped to be able to move segment by segment in an erro free position, but it did not snap there or get " DRC marked free". So I tired the "repair selected" and WOW, it repaired the whole trace, exept the last segment (not possible to move the end point handle). This almost fits all of our requests. Sure, snapping into the right position when moving a segment is missing, but maybe Mentro improves this later on.

For sure we have to look on this feature in more detaile but thats definitively the right way to go.


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In this post and some following ones, I want to bring up the issues and questions that customers brought up to me during the U2U meetings. This includes not only during the BGA Fanout workshop, the Expedition PCB Update presentation, but also in meetings with individual customers.

1. Display Control Scheme Naming - When the user applies a scheme to Display Control and then makes an edit and wants to save and overwrite the original scheme, today the user has to either hunt for the scheme name or remember it and properly type it in the name field. It would be better for the GUI to remember the last scheme name and have that as the default entry.

    • Answer: We are in the process of enhancing our schemes and this is one of the items being addressed. Target date for delivery is not set yet.

2. Grids - In Display Control if you turn off the visibility of a grid, the snapping to the grid is also turned off. We should use the Editor Control and toolbar on/off for snapping of the grid, not Display Control.

    • Answer: We are in the process of enhancing Display Control dialog and this is one of the items being addressed. Target date for delivery is not set yet.

3. User Properties in Cells - One of the enhancements to cells in EE2007.3 is the ability to add user-properties. The question was if these user-properties were available in Drawing and Mechanical cells as well as Package cells.

    • Answer: In EE2007.3, user-properties are only available in Package cells.
    • Question for Customers: Do you have a need to include user-properties in Drawing and/or Mechanical cells?
http://communities.mentor.com/mgcx/servlet/JiveServlet/downloadImage/38-1076-1251/AA.bmp
4. Curved Multiplow - I showed a slide in which curved, any-angle Multiplow was introduced in EE2007.3. The question is, "Which licence is required for this functionality?"
    • Answer: The Flex license is required to support curved Multiplow; however, any-angle Multiplow is available in the standard Pinnacle license.
http://communities.mentor.com/mgcx/servlet/JiveServlet/downloadImage/38-1076-1252/AAA.bmp
That's all for right now, more questions, issues and answers coming up!

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We have used the Edison incandescent light now for over 100 years. But, unfortunately, most of the power goes for heat and not light. The EPA says that if each US home replaced just ONE (1) incandescent light bulb with a solid state illumination LED (SSI), the USA would save more than $600 million in annual energy costs and prevent greenhouse gases equivalent to the emissions of more than 800,000 cars.

Some of the advantages of SSI LEDs are:

  • 50,000 hours MTBF
  • LEDs are in 'mission-critical' applications already like street lights, traffic lights, automobile tail lights (soon to be headlights), stadiums and billboards, LCB backlights and for medical effects
  • 70% efficiency (82 lumens/watt) compared to incandescent at 15% (17 lm/w) and compact fluorescent at 48-60 lm/w
  • A 100 watt incandescent bulb is 1750 luments, a 3 watt HB LED is only 240 lumens for the same lighting effect
  • LEDs can be color corrected to match sunlight
  • In less than 5 years SSI will be 150 lm/w and in the range of $2.00 - $7.00 each
  • There already are LEDs that work off of 117 VAC
  • Organic Light-Emitting Diode (OLED) displays are now in mobile phones and TVs
  • Compact fluorescent lights (CFL) have 3 to 5 milligrams of mercury and a difficulty in matching sunlight

I think that Solid State Illumination (SSI) or high brightness LEDs will be a BIG NEW business for the electronics industry. What do you think?

ADDITION:

David Carey of Portelligent just did a 'tear-down' of a CFL and a HB-LED of about 75 W rating. The CFL was sub-$5 but the HB-LED was ~$80 !! If you look at the photo from the article (http://www.eetimes.com/showArticle.jhtml;jsessionid=OXGNBXT450B1MQSNDLPSKHSCJUNN2JVN?articleID=210604761) below, the HB-LED must have been built for some'rugged' application. But both have circuit boards in them!!

YES, indeed, COST will be the driver but my money is still on the 110VAC HB-LED technology!

1544chart_pg45.jpg

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I had the opportunity to present a paper at the Mentor U2U in Santa Clara on Improving Yields with Advanced DFT. The paper is available from the Mentor web site if you would like to view it.

I had a number of questions afterwards from different customers asking about Design For Test guidelines, specifically in the area of boundary scan.

I am interested to know how you are incorporating boundary scan in to your designs, which boundary scan tool you are using and what feedback mechanism you use to work with Test Engineering to accommodate their requirements.

Thanks

Mark

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Obviously in a downturn both people and companies spend less money. So what does this mean to the electronics industry? I believe that instead of pulling back, electronics companies have to charge forward with more aggressive designs to compete for the limited spending by consumers (either consumer products for personal use or products that serve other industries, depending on your company's target market).

So your bosses are going to pressure you to be more aggressive and creative and design products that will beat your competition. At the same time, your bosses will be pressured to reduce development costs (or produce more products with the same costs) and manufacturing costs since their budgets might get cut. So faster, more functionality, better quality products to market quicker while reducing development costs and reaching production volumes out of the starting gate (target yields in manufacturing). So how does Mentor fit into all of this?

The Systems Design Division of Mentor is delivering innovative PCB design tool technology at a faster rate than ever before. Some of these enhancements to our flows can give our users quantum improvements in designer productivity while enabling them to use the most advanced PCB fabrication technologies and the hottest new ICs and FPGAs. But we find that only the most aggressive of our customers actually stay current with the new releases and take advantage of the latest improvements. We had one customer this year cut their PCB design time by >70% simply by adopting the 2007.1 release.

So if you are a current Mentor user, take advantage of what we are developing by adopting the latest releases. If you have another PCB design system, take a hard look at Expedition Enterprise or Board Station XE. You might help your company's bottom line in hard times.

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What a honor. Henry invited me being the first non Mentor blogger in this community.
My company had a lot of activities together with Mentor Graphics during the last years and most of them were very productive.Many of the community users see the results in their software releases and we are very proud being a part of it.

I probably will find many people again here inside the community I met during the last years and for sure we will have a large number of discussions about software and the areas of improvement..

We just installed the 2007.2 uptdate 6 and now let's see what's inside. (I have to increase my DR counter ;-) )

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I happened to be on the MICROCHIP web site downloading and testing their SPICE models for HyperLynx Analog when I came across the PIC microcontroller. I decided to go ahead and order their PICKit 2 starter package (the cost was right :) )

It's been a while since I have done any assembly level programming and I reckon I had an itch that needed some scratching. To give you and idea of how long, the last microcontroller development system I purchased was the Rockwell AIM 65 (6502 based). I have it sitting here in a box and every couple of years I break it out, consume the kitchen table and have a little fun.

The PICKit 2 arrived last Thursday and I was amazed when I unpacked it... it is so tiny! No more consuming the kitchen table... it fits neatly on my desk in front of my laptop. That would be both the programmer and the development board consuming no more than 2.5 in x 7 in of desktop space. The programmer is USB based and connects to a 6 pin header on the development board. It really is a sweet little package.

MICROCHIP does a fantastic job supplying software, examples, datasheets, application notes... everything you need to get going. In fact, the Integrated Development Environment (IDE) MPLAB is AMAZING!! It includes comprehensive development tools including a language sensitive editor, Instruction Set simulator, debug and device programming capabilities in a well organized and easy to use interface. MPLAB is also FREE to download off of the MICROCHIP site!

The development board contains a 16F690 20 pin PIC microcontroller. This is a Flash based device that has Analog to Digital converters, timers, built-in oscillator, EEPROM, Watchdog timer, Brow-out reset, RAM registers, and a nice allocation of program memory. What was amazing to me was how inclusive the PIC is, you really only need a 6 pin header (for programming) and a power supply capacitor to configure the microcontroller... you don't need an external oscillator although it is configured to accept one.

The PIC architecture is a Harvard based RISC architecture originally designed by General Instruments in 1971. The PIC 16F690 is a 14 bit instruction design with approximately 36 instructions. I took a look on the DigiKey site and the cost is extremely reasonable at $3.05 for single units.

Today is Saturday and I have the instruction set well understood, the Analog to Digital capability operational, complete control over the bi-directional ports and I am ready to make significant progress on my needful project.

One year ago I decided that I was going to design and build a power generating windmill. Over the summer I completed the fabrication and erected my first 40 foot tower with a 10 foot diameter windmill... it was pure dedication that allowed me to complete the project. A couple of weeks ago the wind really kicked up (60+ MPH) and my home made composite blades snapped sending one of the blades over 300 feet away. So, while I was redesigning my blades and hub I decided that I needed some form of feedback control system to pulse brake the windmill in extreme wind conditions. I started the design as a pure analog design (since that is where my current skill set is strongest) and I was running into some interesting boundary challenges as the alternator I built increases in voltage and current as the wind speed increases causing my frequency monitor design to increase in complexity. While I was enjoying the design challenge I was not looking forward to the fabrication as I like to keep my designs very simple. The introduction of the PIC microcontoller into my design will not only simplify my frequency monitor design but will also provide useful in extending my design to include some smart pulsed battery charging techniques as well.

Yes, this blog had really nothing to do with Mentor Graphics Board Design Tools. Clearly, I use our Board Design suite to do more than create Video Blogs and Workshops!! In the not so distant future expect to see a Video Blog combining my Analog designs with a PIC microcontroller into a PCB designed using the MGC tools. :)

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There is nothing easy about Analog functional design! However, that does not imply that learning a new PCB functional simulation tool should be difficult!

If you have been following my Blogs you will see that I have been attempting to provide Video Blogs. The challenge is providing high resolution video over the internet on-demand and quite honestly while I do record high resolution once the Videos have been uploaded and magically massaged through compression algorithms the resulting resolution is disappointing :(

Fortunately, I am a decedent of that rough & ready community that simply refuses to give up. Through the adoption of new Web 2.0 technologies I think we may have achieved a break through and produced the step by step instructions in a high resolution format that will service your quick adoption needs:


    • Workshop 1 takes you all the way through the import of a component Vendor web based SPICE model, circuit creation, simulation setup to analyzing the simulation results => A comprehensive overview


    • Workshop 2 builds on the results of Workshop 1 demonstrating DxDesigner's ability to explore multiple circuit topologies within a single project, simulation test bench management as well as advanced waveform calculations

Tell me what you think! Am I drinking my own cool-aide or does this format provide the high resolution, on-demand, assistance you need to quickly adopt new powerful technologies?

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Folks,

Are you aware that there is a PCB DFF Analysis option for available for Expedition PCB, BSXE and FabLink XE?

Did you know that it provides around 200 hundred or so DFF specific checks that can be run anytime within your PCB design where you can identify the potential problems AND fix them at source. No costly or lengthy round tripping to 3rd party applications here and you have the satisfaction of retaining control over your design data before exporting the manufacturing outputs.

I have posted a couple blogs over the last month or so, discussing some of the challenges related to the PCB design to manufacturing process.

To date, even though I have many hundreds of hits in terms of views, only a few people have actually posted a reply directly or through a related discussion.

This leads me to believe that either:

  • my blogs have really not been that interesting and have not resonated with the community as a whole, (but I don't believe this) or

  • most of you are just to shy and are backward in coming forward with your comments:)

So I am going to resort to an age old technique to attempt to attract you attention with bribery!

Who would like to see a webcast (at their convenience) of the capabilities of the PCB DFF Analysis option for Expedition PCB, BSXE and FabLink XE?

Below is a simple voting mechanism that will allow you to remain anonymous while expressing your interest or not. This will also alleviate my need to keep checking the blog and my email and tallying up the votes every day.

I would like to see a PCB DFF Analysis webcastI would like to see a PCB DFF Analysis webcast

I'll record an on demand webcast and provide the link in a later post so that you can take look whenever find time.

If this does not work, then I suppose I'll have to borrow some creative writing tips from Dave Brady!!! Please spare me that. :)

Best Regards,

Steve

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A while back we wrote about the need and recent development of collaboration capabilities between the PCB (ECAD) designer and the mechanical (MCAD) designer. The establishment of the EDMD industry standard and initial capabilities by Mentor and PTC have added the ability to bi-directionally communicate and negotiate incremental changes between the domains. Dr. Russ Henke commented on the capability in his blog:

http://cofes.com/Community/Blogs/tabid/272/EntryID/158/Default.aspx

And later, Gabe Moretti's blog commented on Mentor's acquisition of Flomerics (primarily supporting the MCAD domain):

http://www.edadesignline.com/blogs/

This blurring of what were once two distinct disciplines (ECAD and MCAD) by creating collaboration and shared analysis capabilities is only one step in improving the efficiency of an electronics company's product development process. There is more to a product than a PCB and an enclosure. There are still opportunities as Mentor continues our focus on the PCB systems design improvements but pursues additional collaboration facilities to other domains. Collaboration opportunities include:

  • FPGA/PCB co-design - focus on improving performance at the system level
  • ASIC/Package/PCB - optimizing ASIC package and SiP package pin-outs
  • PCB to procurement and manufacturing - increasing yields and shortening time-to-volume production
  • Collaboration within PCB systems design - concurrent schematics and rules entry, simultaneous design by dispersed teams, RF/analog/digital co-design
  • EE to PCB CAD - power delivery systems, simultaneous PCB layout and high speed analysis

With today's pressures on electronics companies to continue to tighten their belts, these types of product development efficiencies will only help them to stay ahead of their competition while meeting their aggressive business goals.

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Monte Carlo Analysis is a powerful technique to analyze your PCB design against the tolerances of the components you may expect from your component supplier. Performing Monte Carlo analysis could easily save you substantial amount of money and greatly improve your production manufacturing yield by identifying appropriate component tolerances.


If you found this Video Blog useful let me know by leaving a comment|

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This morning I was sent the following comment (name changed to protect the innocent):

I don't need Mentor to fix anything because I don't do "crappy" work. (Actually a different term was used, but not appropriate for this forum). I don't do DRC or if I do I ignore the errors and warnings. I just export the gerber files and examine them. DRC is for those who don't want to learn how to layout a PCB or those that are hired from the street corner.
Just my opinion.
Joe
At first glance, my reaction to this is that this fellow should not be using Mentor tools, he should use AutoCAD.

After second thought however, it is clear to me that every designer draws a line to define a threshold in terms of what they expect the software to manage and what should be left up to the designer. For example, I am quite sure that Joe would not like it if when moving a part, we did not move the padstacks with it. So at some level he expects the software to be correct-by-construction. Joe appears to have drawn a line where he wants to craft every trace manually. So I now wonder if he has timing requirements - does he expect any feedback to tell him if the delays are as desired? Does he expect that we will keep diff pairs together? Or maybe he doesn't define diff pairs and just routes them close together as he sees fit?

So, in the end, every designer assumes that the software will automatically manage the design to a certain extent. As a software vendor however, we need to have software flexible enough so that the system can be tuned to draw that line at the "right" place and allow the designer the freedom to craft as desired.


Where do you draw that line? Are your boards so big and complex that the only way they can be completed on schedule is with a very high level of DRC and automatic management of constraints? Or are your designs simple enough that you don't want any DRC? Or maybe it doesn't matter how complex your designs are, your boss requires full and complete DRC with every project? Please provide some feedback, it will help us understand better what our customers need to be successful.


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This is a "COOL" technology. Imagine being able to 'print' transistors on 'paper' and other materials.

The bulk of the investment in printed electronics has been taking place in the West, including many factories coming on stream in 2007. This is well reported. However, there is now a surge of investment in printed electronics in Asia and many giant companies have entered the field for the first time. East Asian activity is poorly reported in the main but nonetheless very significant, because in East Asia they have much at stake. Asia already dominates in OLED production, with huge production and investment. The next generation of OLEDs will be flexible and printed and Asia must hold on to that too. China is now the world's largest user of RFID and it will shortly be the largest supplier and these tags are increasingly printed. Indeed, even the silicon chip in them will be replaced with printed logic at one hundredth of the cost, so trillions can be sold every year.

There are a remarkable 37 organisations working on printed transistors in Asia, with breakthroughs such as printable amorphous Ga In Zn O invented in Japan, one organization driving OLEDs with polymer transistors and another commercializing light emitting transistors. The plastic film scanner with no moving parts, e-skins, power sheets, various forms of electronics in biodegradable paper, a flexible organic battery that charges in only one minute, plastic film that acts as an ultrasonic transducer and plastic "e-paper" flexible displays are among the many new inventions being commercialized in the region.

I wonder if this type of electronics uses IC EDA tools or PCB EDA tools - - or a new hybrid of both?

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The parametric test system (PTS) was created by Hewlett-Packard's Printed Circuit Division in 1987 based on early H-P coupons used in production since 1972. Those early coupons focused on inner-layer shifting, by using the copper on I/Ls shorting to a PTH, moiré patterns, and hole quality cross-sections. Additional influence came from a parametric printed circuit board used as a training and process vehicle for the first NanYa PCB Facility in Taiwan (circa 1983). This PCB had various design-rule technologies on it and provided feedback on how the process was improving.

The H-P PTS was a group of seven coupons that could be placed on production panels or used on parametric panels to provide a snapshot of the capability of the processes. The initial seven coupons (*Figure 1*) were designed to test:

  • (a) Outer-layer registration
  • (b) Inner-layer registration and shifting
  • (c) Conductors/pads open and shorts
  • (d) Plated through-hole and I/L conductors continuity
  • (e) Artwork defects
  • (f) Soldermask registration
  • (g) Etch factors

The coupons were all designed to be tested by facility continuity testers using a bed-of-nails open-short testing machine. In H-P's case, the tester was an ATG2000 grid tester. The testers fault-file was captured by an H-P workstation and stored. Each coupon had a stored perfect response or netlist that was compared to the fault file and the opens and shorts were translated to dimensional shifts or other parametric data. The RS/1 statistics program was used to produce control charts and statistical reports, as well as historic data. To provide for process control, the coupons were reduced in size and small stand-alone coupon testers were built to allow operators to check the process immediately as a confidence indicator. These home-built milliohm meters worked with a simple 1-amphere power brick, a 4-digit digital panel meter and a machined-Plexiglas coupon holder with 8-spring-loaded gold pins wired to a 4-position rotary switch in a 4-wire Kelvin measurement scheme.

The Gerber artwork for these 7 PTS coupons are in the ZIP file at the end of this BLOG.

Slide26.JPG

Slide14.JPG


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