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Recent Content

Subject Author
Re: Synthesis Design Optimization techniques (Precision RTL) 7 hours ago in Design and Synthesis by Hans Hans
Re: Modelsim vcover merge problem 8 hours ago in General by Hans Hans
Re: Panelization in-house or at pcb supplier? 10 hours ago in Board Fabrication, Assembly and Manufacturing by Andreas.Schaefer Andreas.Schaefer
Re: Part Height report 10 hours ago in Automation and Scripting by Andreas.Schaefer Andreas.Schaefer
Re: Connector related parts 10 hours ago in VeSys 2.0 by Simon Simon
Re: How to edit the wire table in a harness design? 11 hours ago in VeSys 2.0 by Simon Simon
Re: How to remove text in a border (VeSys 2.0 Symbol) 14 hours ago in VeSys 2.0 by Boudewijn Boudewijn
Modelsim vcover merge problem 14 hours ago in ASIC/FPGA Design by chiranjeevi chiranjeevi
Re: Locked out of project 15 hours ago in VeSys 2.0 by Simon Simon
Re: What is a good way to back-up Designs in VeSys 2.0? 16 hours ago in VeSys 2.0 by Simon Simon
Script don't work : Split function 17 hours ago in Automation and Scripting by janggj janggj
Re: How do you make a new library database without any parts inside it? 18 hours ago in VeSys 2.0 by ashish_wadhwa ashish_wadhwa
Re: How do you delete parts from the component maintenance library? 18 hours ago in VeSys 2.0 by ashish_wadhwa ashish_wadhwa
Re: XML from Components into Access 1 day ago in How do I use VeSys? by Nuri Nuri
Re: Print the contents of the browser tree? 1 day ago in CHS Design Tasks by ashish_wadhwa ashish_wadhwa
Re: I have a question about Catapult (area unit) 1 day ago in ESL - Electronic System Level by hamoudiz hamoudiz
Re: Have you joined the displaced worker program yet? 1 day ago in Displaced Worker Training Program by Peruzzi Peruzzi
Re: Siemens PLM Teamcenter Interface compatability 2 days ago in VeSys 2.0 by phil_davies phil_davies
Re: Nets not connected after copper pour 2 days ago in PADS - Desktop PCB Design by Daniel_Lange Daniel_Lange
Failed to connect to CES using VB 2 days ago in Automation and Scripting by navit.alaouf navit.alaouf
Re: DRC error in ICstation 3 days ago in DRC, LVS, Parasitic Extraction - Calibre by chris_balcom chris_balcom
Balaji seeking a ASIC Design/Validation/Verification position 3 days ago in Jobs Wanted by bbalasub bbalasub
Catapult will support control synthesis and power optimization in the next release 3 days ago in ESL - Electronic System Level by Din Din
Automatic stitching vias placement around a trace in Expedition 4 days ago in Layout and Routing by bbpcbdesign bbpcbdesign
Re: SystemC Japan 2009 4 days ago in 日本語 - IC, PCB, ASIC/FPGA, Harness by BigMama BigMama
Re: Source Names That Appear On More Than One Object 4 days ago in DRC, LVS, Parasitic Extraction - Calibre by karthikm karthikm
Re: launch simalution failed from Catapult C SCverify : error altera_mf not found 5 days ago in ESL - Electronic System Level by hamoudiz hamoudiz
Re: Question:Supported Language feature in CatapultC 6 days ago in ESL - Electronic System Level by kha_ayoub kha_ayoub
Re: Help with Netlist Verification 1 week ago in Design and Synthesis by vijay_madhavan vijay_madhavan
Re: calibre question --how to get bondpad coordinate 1 week ago in DRC, LVS, Parasitic Extraction - Calibre by chris_balcom chris_balcom
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