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    DFM PROPERTY in LVS command file 3 hours ago in DRC, LVS, Parasitic Extraction - Calibre by andrewng andrewng
    MAPPING 4 hours ago in ESL - Electronic System Level by sunlight2312 sunlight2312
    Re: Differential pairs,rescheduling,diff pair drc errors, staggered pin connectors and trying to get these bugs fixed in the router. 5 hours ago in Ask the PADS Team by robert_davies robert_davies
    Re: Cloud-Based Solution in the EDA 6 hours ago in Expedition Enterprise - Enterprise PCB Design by Rapport Rapport
    Write leveling result in DDR3 batch simulation 7 hours ago in Ask the HyperLynx Expert by zhenshui.qin zhenshui.qin
    Re: unable to open iCDB connection, No Server is runing for the project and could not bring it alive 16 hours ago in Ask the DxDesigner Expert by andrew_audova andrew_audova
    Re: Hyperlynx DRC 17 hours ago in HyperLynx - Simulation and High-Speed Design by Steve_McKinney Steve_McKinney
    Re: How to Speed UP  the access to Libraries in the server? 19 hours ago in Library and Data Management by jeff.heidel jeff.heidel
    Re: ROM usage 20 hours ago in ESL - Electronic System Level by rlihakanga rlihakanga
    Re: Will moving a cell to a different partition affect users? 20 hours ago in Library and Data Management by David_S David_S
    Re: Are Jenkins master slave connections allowed with nodelocked uncounted licenses? 21 hours ago in Licensing and Installation by ben_painter ben_painter
    Re: about connectivity inheritance 21 hours ago in DRC, LVS, Parasitic Extraction - Calibre by samantha_lizak samantha_lizak
    Re: Castellated/Half-Via Mounting Holes - Design info request 21 hours ago in PADS Layout and Routing by jduquette jduquette
    Re: How to find global signals in Dx project? 22 hours ago in Automation and Scripting by john_dube john_dube
    Re: idf Import into PADS 22 hours ago in PADS Layout and Routing by Robert_Yoder Robert_Yoder
    Re: 9.4.1 Update 1 day ago in PADS Front-end Design (DxDesigner, PADS Logic) by davep davep
    Re: Translation of Multi-Part Component from Alitum Designer 1 day ago in Ask the DxDesigner Expert by louis.mcgee louis.mcgee
    Each layer view in PADS 1 day ago in PCB Viewers by takeshi.ono takeshi.ono
    Re: Tool for the EDA Tools report generation 1 day ago in Licensing and Installation by nitin.gizare nitin.gizare
    Re: How could i found the meaning of these messages? 1 day ago in ESL - Electronic System Level by sima2050 sima2050
    Rotated Component Clearance script 1 day ago in Automation and Scripting by john_dube john_dube
    Some techniques for wrapping the algorithmic C++ code with SystemC to build and integrate the design 1 day ago in ESL - Electronic System Level by AK AK
    Re: Please help with 9.4.1 !!! 1 day ago in PADS Layout and Routing by benny1 benny1
    Ring Terminal Symbol orientation question 1 day ago in VeSys 2.0 by maria_smith maria_smith
    Is there a limit to the number of connector symbol views in VeSys2.0? 1 day ago in VeSys 2.0 by maria_smith maria_smith
    Mapping 1 day ago in ESL - Electronic System Level by sunlight2312 sunlight2312
    Re: DDRx Wizard Simulation Setup for PLL Only Topology (Hyperlynx 8.1) 1 day ago in Ask the HyperLynx Expert by weston_beal weston_beal
    Re: Passing variables/parameters when running scripts 1 day ago in Automation and Scripting by aldiaz aldiaz
    Re: EULA Site Definition 1 day ago in PADS Layout and Routing by Andreas.Schaefer Andreas.Schaefer
    Re: Two questions when use Vesys 2.0 for design work 2 days ago in VeSys 2.0 by zhigang_xu zhigang_xu
    Re: How to show the <Zone.name> in different drawings when use Vesys_Electrical_2008 2 days ago in How do I use VeSys Classic? by zhigang_xu zhigang_xu
    Re: "AddAttribute" usage in DxDesigner 2 days ago in Automation and Scripting by Dennis_K Dennis_K
    Re: How to force a portion of the code to be executed only one time in Catapult C Synthesis ? 2 days ago in ESL - Electronic System Level by AK AK
    Re: Importing Wire to-from list from .xls or .csv file 3 days ago in VeSys 2.0 by Joel_Pointon Joel_Pointon
    Re: Ribbon Cables within VeSys 3 days ago in VeSys 2.0 by Nuri Nuri
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