Mentor Graphics Communities

A Place to Learn, Share, and Network.

Announcement: Sign Up NOW ! Receive Community Email Updates right to your Mailbox !

Subject		Author
	Re: Automation and Perl 3 hours ago in Automation and Scripting	by lary.e
	Re: container controls 4 hours ago in Automation and Scripting	by bparise
	Questions about DxDataBook and PDB 8 hours ago in Expedition Enterprise - Enterprise PCB Design	by yth_0
	Re: Virtuoso/Calibre RVE set context 11 hours ago in DRC, LVS, Parasitic Extraction - Calibre	by gford
	Re: DRC Question 19 hours ago in Ask the DxDesigner Expert	by robert_davies
	Re: Nelist tool functionality changed between ePD2005 and EE2007. 20 hours ago in Ask the DxDesigner Expert	by avjohn
	Re: Request for a script that reads in an LVS rules file (SVRF) and outputs TRACE PROPERTY statements for every property on each defined DEVICE? 22 hours ago in DRC, LVS, Parasitic Extraction - Calibre	by Tricia_Allgyer
	Re: Are special features lines required (license file) to run FPGA Boardlink in Design Architect 23 hours ago in FPGA to Board	by JeanDu
	Re: Automation for printing a searchable PDF from Design Capture 1 day ago in Automation and Scripting	by lary.e
	Re: moves all the assembly references to the origin and changes the height and orientation 1 day ago in Automation and Scripting	by bparise
	Re: Read and manipulate Part Attributes in PADS Libraries 1 day ago in Automation and Scripting	by esko.leppanen
	Re: Importing a DSI into VeSys Classic 1 day ago in How do I use VeSys Classic?	by mike_templeman
	Re: Scout numbers sheets differently in EE2007 than it does in ePD2005. 3 days ago in Ask the DxDesigner Expert	by yu.yanfeng
	Re: How can I combine 6 parts and a 2-D line? 3 days ago in Ask Andy	by yu.yanfeng
	Re: Have you joined the displaced worker program yet? 3 days ago in Displaced Worker Training Program	by Mentor_Christine
	Re: warnings messages during calibreview generation 3 days ago in DRC, LVS, Parasitic Extraction - Calibre	by karen_chow
	Re: The .p export file from the PADS library 3 days ago in Ask Andy	by brian1
	What Means That Mentor Acquries Zeland's IE3D-SI? 3 days ago in Signal and Power Integrity, EMI, EMC and more	by yu.yanfeng
	Re: Can Calibre do LVS for a Cadence design with mixed schematic view and CDL netlist view? 4 days ago in DRC, LVS, Parasitic Extraction - Calibre	by chris_balcom
	Power Plane and Ground plane copper pour problem: positvie copper pour on negative CAM layer? 4 days ago in PADS - Desktop PCB Design	by wgao
	ODB++ output of solder and paste mask 5 days ago in PADS - Desktop PCB Design	by k.hofmann
	Re: Cell Editor Problem 5 days ago in Expedition Enterprise - Enterprise PCB Design	by tligotti
	Samba Server 5 days ago in PADS - Desktop PCB Design	by brian1
	Re: Circuit count and bundle size 6 days ago in VeSys 2.0	by Nuri
	Re: Pre-defined RF structures in DxD flow 6 days ago in Design Creation and Electrical Constraints	by lennart.granlund
	Re: Automation and VB.net 6 days ago in Automation and Scripting	by Satoru
	Re: WARNING: Net "/MAX_ERROR_LED" is being renamed to "/LTC_SET" to match the change? 6 days ago in Ask the Expedition Enterprise Insider	by yu.yanfeng
	Creating a DxDesigner Readonly shortcut 6 days ago in Automation and Scripting	by Gary_Lameris
	Re: Why does my Calibre DESIGNrev become very slow when loading? 1 week ago in Calibre Viewers	by tom_donnelly
	Re: autoroute power and ground 1 week ago in PADS - Desktop PCB Design	by sharrison