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78,671 Views 6 Replies Last post: Oct 22, 2010 12:00 PM by Guy RSS
deepa1206 Contributor 15 posts since
May 1, 2009
Currently Being Moderated

Oct 21, 2010 12:17 AM

Determine critical path of circuit

Hi
Can anyone please tell me if it is possible to find critical path of a circuit using only ModelSIM? I have a combinational logic block  with 8 inputs and want to simulate all possible input combinations to see which takes the maximum time.
Are there any commands/menu options available for that? I searched the internet and could not find any info.
Thanks
Hans Aficionado 104 posts since
Aug 27, 2008
Currently Being Moderated
Oct 21, 2010 12:54 AM in response to: deepa1206
Re: Determine critical path of circuit

Hi Deepa,

 

I don't believe there is any. However, you might be able to create a Tcl script that measures the time between 2 events (or cursors). Check the reference manual for the "when", "examine" and "wave cursor" commands.

 

I assume you have coded your combinatorial circuit out of primitives and associate delays, if not then I would suggest you try the synthesis route again since it might be a lot easier and more accurate.

 

Good luck,

Hans.

Guy jedi 289 posts since
Apr 1, 2008
Currently Being Moderated
Oct 21, 2010 11:19 AM in response to: deepa1206
Re: Determine critical path of circuit

Is this for an FPGA or an ASIC?

Guy jedi 289 posts since
Apr 1, 2008
Currently Being Moderated
Oct 22, 2010 12:00 PM in response to: deepa1206
Re: Determine critical path of circuit

You should have access to the Precision synthesis tool through the Mentor University Program. Just run your simple example through "compile" in Precision. From there you can use a virtual clock to set input and output delays on the combinatorial paths

 

 

compile
create_clock -domain Design_Clock -name vclk -period 25 -waveform { 0 12.5 } -design rtl
set_input_delay 6.000 -clock vclk -add_delay -design rtl a
set_input_delay 6.000 -clock vclk -add_delay -design rtl b
set_output_delay 4.000 -clock vclk -add_delay -design rtl o

 

Check the "Specifying Input to Output Delay" section in Chapter 3 of the Precision User's Manual for details. Once the constraints are set, you can generate a timing report for the pre-synthesized design:

 

 

report_timing -from b
...
...
# Info: Critical path #1, (path slack = 13.000):
# Info: SOURCE CLOCK: name: vclk period: 25.000000
# Info: Times are relative to the 1st rising edge
# Info: DEST CLOCK: name: vclk period: 25.000000
# Info: Times are relative to the 2nd rising edge
# Info: NAME         GATE       DELAY    ARRIVAL DIR  FANOUT
# Info: b         (port)                 6.000   dn
# Info: b         (net)        0.000                   1
# Info: ix3/in[1] AND2                   6.000   dn
# Info: ix3/out   AND2         1.000     7.000   dn
# Info: o_0n0s2   (net)        0.000                   1
# Info: ix1/in[0] AND2                   7.000   dn
# Info: ix1/out   AND2         1.000     8.000   dn
# Info: o         (net)        0.000                   0
# Info: o         (port)                 8.000   dn
# Info: Initial edge separation:     25.000
# Info: Source clock delay:      -    0.000
# Info: Dest clock delay:        +    0.000
# Info: -----------
# Info: Edge separation:             25.000
# Info: Setup constraint:        -    4.000
# Info: -----------
# Info: Data required time:          21.000
# Info: Data arrival time:       -    8.000   ( 100.00% cell delay, 0.00% net delay )
# Info: -----------
# Info: Slack:                       13.000

 

I think most of the primitive cells have a cell delay of 1, so you could play around with the input and output delays. Or you could add some max delays

 

 

set_max_delay -from a -to o 2

 

 

# Info: Critical path #1, (path slack = -10.000):
# Info: SOURCE CLOCK: name: vclk  Path is min/max delay constrained
# Info: NAME         GATE       DELAY    ARRIVAL DIR  FANOUT
# Info: a         (port)                 6.000   dn
# Info: a         (net)        0.000                   1
# Info: ix3/in[0] AND2                   6.000   dn
# Info: ix3/out   AND2         1.000     7.000   dn
# Info: o_0n0s2   (net)        0.000                   1
# Info: ix1/in[0] AND2                   7.000   dn
# Info: ix1/out   AND2         1.000     8.000   dn
# Info: o         (net)        0.000                   0
# Info: o         (port)                 8.000   dn
# Info: Minmax delay constraint:      2.000
# Info: Source clock delay:      -    0.000
# Info: Dest clock delay:        +    0.000
# Info: -----------
# Info: Edge separation:              2.000
# Info: Setup constraint:        -    4.000
# Info: -----------
# Info: Data required time:          -2.000
# Info: Data arrival time:       -    8.000   ( 100.00% cell delay, 0.00% net delay )
# Info: -----------
# Info: Slack (VIOLATED):           -10.000

 

Then you could set some multi-cycle paths to see how they effect the timing

 

 

set_multicycle_path -from b 2
report_timing -from b
...
...
# Info: Critical path #1, (path slack = 38.000):
# Info: SOURCE CLOCK: name: vclk period: 25.000000
# Info: Times are relative to the 1st rising edge
# Info: DEST CLOCK: name: vclk period: 25.000000
# Info: Times are relative to the 2nd rising edge
# Info: NAME         GATE       DELAY    ARRIVAL DIR  FANOUT
# Info: b         (port)                 6.000   dn
# Info: b         (net)        0.000                   1
# Info: ix3/in[1] AND2                   6.000   dn
# Info: ix3/out   AND2         1.000     7.000   dn
# Info: o_0n0s2   (net)        0.000                   1
# Info: ix1/in[0] AND2                   7.000   dn
# Info: ix1/out   AND2         1.000     8.000   dn
# Info: o         (net)        0.000                   0
# Info: o         (port)                 8.000   dn
# Info: Initial edge separation:     25.000
# Info: Source clock delay:      -    0.000
# Info: Dest clock delay:        +    0.000
# Info: -----------
# Info: Edge separation:             25.000
# Info: Multicycle adjustment    +   25.000
# Info: -----------
# Info: Edge separation:             50.000
# Info: Setup constraint:        -    4.000
# Info: -----------
# Info: Data required time:          46.000
# Info: Data arrival time:       -    8.000   ( 100.00% cell delay, 0.00% net delay )
# Info: -----------
# Info: Slack:                       38.000
# Info: Multicycle adjustment of 25.000000 was made for this path
# Info: End CTE Analysis ..... CPU Time Used: 0 sec.

 

For the net delays, you could use set_max_delay -through to fake the net delays for specific paths

 

 

set_max_delay -through ix3.out 7
report_timing -from b
...
...
# Info: Critical path #1, (path slack = 38.000):
# Info: SOURCE CLOCK: name: vclk period: 25.000000
# Info: Times are relative to the 1st rising edge
# Info: DEST CLOCK: name: vclk period: 25.000000
# Info: Times are relative to the 2nd rising edge
# Info: NAME         GATE       DELAY    ARRIVAL DIR  FANOUT
# Info: b         (port)                 6.000   dn
# Info: b         (net)        0.000                   1
# Info: ix3/in[1] AND2                   6.000   dn
# Info: ix3/out   AND2         1.000     7.000   dn
# Info: o_0n0s2   (net)        0.000                   1
# Info: ix1/in[0] AND2                   7.000   dn
# Info: ix1/out   AND2         1.000     8.000   dn
# Info: o         (net)        0.000                   0
# Info: o         (port)                 8.000   dn
# Info: Initial edge separation:     25.000
# Info: Source clock delay:      -    0.000
# Info: Dest clock delay:        +    0.000
# Info: -----------
# Info: Edge separation:             25.000
# Info: Multicycle adjustment    +   25.000
# Info: -----------
# Info: Edge separation:             50.000
# Info: Setup constraint:        -    4.000
# Info: -----------
# Info: Data required time:          46.000
# Info: Data arrival time:       -    8.000   ( 100.00% cell delay, 0.00% net delay )
# Info: -----------
# Info: Slack:                       38.000
# Info: Multicycle adjustment of 25.000000 was made for this path

 

Or if you targeted something like an Actel 40mx, you could run "synthesize" and use the values from the library for the cell and net delays

 

 

setup_design -manufacturer Actel -family 40MX -part A40MX04PQ100 -speed -F
setup_design -addio=false
...
compile

create_clock -domain Design_Clock -name vclk -period 25 -waveform { 0 12.5 } -design rtl
set_input_delay 6.000 -clock vclk -add_delay -design rtl a
set_input_delay 6.000 -clock vclk -add_delay -design rtl b
set_output_delay 4.000 -clock vclk -add_delay -design rtl o

synthesize

report_timing -to o -show_nets -show_schematic
...
Critical path #1, (path slack = -18.501):

SOURCE CLOCK: name: vclk  Path is min/max delay constrained

NAME         GATE       DELAY    ARRIVAL DIR  FANOUT
a         (port)                 6.000   dn
a         (net)        0.000                   1
o_0n0s2/A AND2                   6.000   dn
o_0n0s2/Y AND2         4.573    10.573   dn
o_0n0s2   (net)        1.355                   1
o/B       AND2                  11.928   dn
o/Y       AND2         4.573    16.501   dn
o         (net)        0.000                   0
o         (port)                16.501   dn

        Minmax delay constraint:      2.000
        Source clock delay:      -    0.000
        Dest clock delay:        +    0.000
                                -----------
        Edge separation:              2.000
        Setup constraint:        -    4.000
                                -----------
        Data required time:          -2.000
        Data arrival time:       -   16.501   ( 91.79% cell delay, 8.21% net delay )
                                -----------
        Slack (VIOLATED):           -18.501

 

crit_path.jpg

 

For me, it is easier to use static timing vs simulation to understand the concept of critical paths. The schematic viewer really helps to visualize what is going on in the circuit too.

Hans Aficionado 104 posts since
Aug 27, 2008
Currently Being Moderated
Oct 22, 2010 12:53 AM in response to: deepa1206
Re: Determine critical path of circuit

Hi Deepa

What do you mean by primitive/associative delays?

When you Synthesize and Place&Route your design you can extract a netlist consisting of primitive elements (basic building blocks of the target technology) and a file containing delay information (SDF). To create a model you can instantiate these primitives in your Verilog and add some delay.

Synthesis will ignore the delays. How can I make synthesis tools use the gate delays that I want?

You can't, the delay is extracted from the Place&Routed design.

 

If I were you I would create a script to generate the different combinations and place them between 2 registers, I would then synthesize the different combinations (also from the script) and extract the Fmax. If you target a modern FPGA you will probably end up with the same Fmax for most combinations, if this is the case and you have access to a vendor neutral synthesis tool then try targeting an old FPGA, for example an Actel A1010.

 

Regards,

Hans.

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